Chip scale package

A chip scale package for packaging an IC chip, comprising:

• an IC chip having a top surface, a bottom surface, and side surfaces extending between said top and bottom surfaces, at least a pair of spaced bonding points being disposed on said top surface of said IC chip;
• a package frame having opposite side walls, each extending along a respective one of said side surfaces of said IC chip, said package frame further having bottom beams extending beneath said bottom surface of said IC chip from a lower portion of said side walls of said package frame, said side walls of said package frame having respective upper portions extending above said top surface of said IC chip, a first gap being defined between said side surfaces of said IC chip and said side walls of said package frame, and a second gap being defined between said bottom surface of said IC chip and said bottom beams of said package frame;
• at least a pair of substantially identical leads electrically coupled to respective said bonding points, and extending therefrom in opposite directions, each of said leads having:
• an inner lead portion attached to said top surface of said IC chip,
• an outer lead portion bent to follow a contour of outside surface of a respective one of said side walls and said bottom beams of said package frame, and
• a connecting segment coupled between said inner lead portion and said outer lead portion and extending in slanted mutual relationship thereto between substantially said top surface of said IC chip and said upper portion of said side walls of said package frame, an angle being formed between said connecting segment and said side walls of said package frame;
• said angle and said first and second gaps defined between said IC chip and said package frame changing in response to induced stress, thereby cushioning said stress.