Data processing device with loop pipeline
AssigneeSiemens Aktiengesellschaft
InventorsRod G. Fleck, Venkat Mattela, Eric Chesters, Muhammad Afsar
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Abstract
The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.
Claims23
Data processing device comprising:
- an instruction providing unit having an input and an output;
- and
- an instruction processing unit being coupled with said output of said instruction providing unit, wherein said instruction processing unit comprises:
- a pipeline unit for processing instructions supplied by said instruction providing unit having input and output stages, wherein said pipeline unit processes a loop instruction on a first occurrence;
- and
- a loop pipeline unit for processing all following occurrences of said loop instruction supplied by said instruction providing unit having input and output stages;
- wherein
- said input stages of said pipeline unit and said loop pipeline unit being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines;
- and
- said pipeline unit and said loop pipeline unit processing said data independently;
- and wherein all units are integrated within a single microprocessor.
A method for executing a loop instruction which is part of a instruction stream in a microprocessor for processing instructions, said microprocessor having an instruction providing unit with an input and an output, a first pipeline unit for processing data with input and output stages, a second pipeline unit for processing a loop instruction with input and output stages, said input stages of said pipeline units are connected to said output of said instruction providing unit, said instruction providing unit providing instructions for said pipelines;
- the method comprises the step of:
- predecoding said instruction stream and providing said first pipeline with the respective instructions, wherein said loop instruction is issued to said first pipeline on its first occurrence and extracting said loop instruction out of the instruction stream on all following occurrences and issuing said loop instruction to said second pipeline unit, said loop instruction being executed in parallel with said other instructions of said instruction stream.
A method for executing a loop instruction including a loop target address and a loop counter value in a microprocessor for processing instructions having a program counter, an instruction providing unit with an input and an output, a loop target buffer being connected to said instruction providing unit, a pipeline unit for processing data with input and output stages, a loop pipeline unit for processing a loop instruction with input and output stages, said input stages of said pipeline units are connected to said output of said instruction providing unit, said instruction providing unit providing instructions for said pipelines;
- the method comprises the step of:
- if a loop instruction occurs for the first time, executing said loop instruction in said pipeline unit and thereby storing loop related data in said loop target buffer;
- wherein after the execution of said loop instruction during execution of said loop, said loop instructions are processed in said loop pipeline.
Dependencies are inferred from the claim text.