Asynchronous transfer mode adapter for desktop applications

An application specific integrated circuit for adapting a user end station to an ATM network, the application specific integrated circuit comprising:

• a bus interface for communicating with the user end station, the bus interface operating at a speed supplied by a bus of the user end station;
• a physical interface circuit for communicating with the ATM network;
• a segmentation engine for segmenting user end station data into ATM formatted data, the segmentation engine communicating with the bus interface to receive user end station data, the segmentation engine further communicating with the physical interface circuit to transfer ATM formatted data to the ATM network;
• a reassembly engine for generating user end station data from ATM formatted data, the reassembly engine communicating with the physical interface circuit to receive ATM formatted data, the reassembly engine further communicating with the bus interface to transfer user end station data to the user end station;
• and
• wherein the application specific integrated circuit is adapted for location at the user end station.

An apparatus for communicating data from a host to an ATM network and for communicating ATM cells from an ATM network to a host, the apparatus comprising:

• a host bus interface circuit for communicating with the host, the host bus interface circuit operating at a speed supplied by a bus of the host;
• a physical interface circuit for communicating with the ATM network;
• a segmentation engine that operates with the host to segment data in a memory into ATM cells and to transfer the ATM cells to the physical interface circuit;
• a reassembly engine that operates with the host to receive ATM cells from the physical interface circuit and to reassemble the ATM cells into data in the memory;
• and
• wherein the host bus interface circuit, the physical interface circuit, the segmentation engine, and the reassembly engine are formed as an integrated circuit for location at the host.

An application specific integrated circuit for adapting a user end station to an ATM network, the application specific integrated circuit comprising:

• a bus interface for communicating with the user end station, the bus interface operating at a speed supplied by a bus of the user end station;
• a physical interface circuit for communicating with the ATM network;
• a segmentation engine that operates with the user end station to segment data in a memory into ATM formatted data and to communicate the ATM formatted data to the physical interface circuit;
• a reassembly engine that operates with the user end station to receive ATM formatted data from the physical interface circuit and to generate user end station data from the ATM formatted data in the memory;
• and
• wherein the application specific integrated circuit is adapted for location at the user end station.

An apparatus for communicating data from a host to an ATM network and for communicating ATM cells from an ATM network to a host, the apparatus comprising:

• a bus interface circuit for communicating with the host, the bus interface circuit operating at a speed supplied by a bus of the host;
• a physical interface circuit for communicating ATM cells with the ATM network;
• a first memory buffer for storing an ATM cell that has been segmented from data in a memory and is awaiting communication to the physical interface;
• a second memory buffer for storing an ATM cell that has been received from the physical interface and is awaiting to be reassembled into data in the memory;
• and
• wherein the bus interface circuit, the physical interface circuit, the first memory buffer, and the second memory buffer are adapted for location at the host.

An apparatus for communicating data from a host to an ATM network and for communicating ATM cells from an ATM network to a host, the apparatus comprising:

• a host bus interface circuit for communicating data with the host;
• a physical interface circuit for communicating ATM cells with the ATM network;
• a segmentation engine cooperating with the host bus interface circuit to receive data from the host, the segmentation engine segmenting the data into ATM cells, the segmentation engine further cooperating with the physical interface circuit for transferring the ATM cells to the ATM network;
• a reassembly engine cooperating with the physical interface circuit to receive ATM cells from the ATM network, the reassembly engine reassembling the ATM cells into data, the reassembly engine further cooperating with the host bus interface circuit for transferring the data to the host;
• a memory interface circuit communicating with the segmentation engine and the host bus interface circuit to support the transfer of data from the host to the segmentation engine and with the reassembly engine to support the transfer of data from the reassembly engine to the host, the memory interface circuit comprising a RAM interface/arbiter circuit;
• a DMA controller circuit communicating with the RAM interface/arbiter circuit to control memory access operations of the RAM interface/arbiter circuit;
• and
• wherein the host bus interface circuit, the physical interface circuit, the segmentation engine, the reassembly engine, the memory interface circuit and the DMA controller circuit are formed as an integrated circuit for location at the host.