Active compensating capacitive multiplier
AssigneeTexas Instruments Incorporated
InventorGabriel Alfonso Rincon-Mora
Life of this patent
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Abstract
A compensated amplifier, for amplifying an input signal applied to an input node to provide an output signal at an amplifier output node. The compensated amplifier includes a first amplifier stage having an internal node as an input thereto and having a first stage output node. Also included is a second amplifier stage coupled to the first amplifier stage, having the input node as an input thereto and providing the output signal at the amplifier output node. A capacitor is coupled between the output node and the internal node.
Claims5
A Miller-compensated amplifier, for amplifying an input signal applied to an amplifier input node to provide an output signal at an amplifier output node, comprising:
- a first amplifier stage having an internal node as an input thereto, and having a first stage output node;
- a second amplifier stage having said amplifier input node as an input thereto, and having a second stage output node;
- a third amplifier stage having a third stage input node coupled to said first stage output node and to said second stage output node, and providing said output signal at said amplifier output node;
- and
- a capacitor coupled between said amplifier output node and said internal node so as to provide voltage-mode gain.
A Miller-compensated amplifier, for amplifying a differential input signal applied to an amplifier input node to provide an output signal at an amplifier output node, comprising:
- a differential amplifier, for converting the voltage of said differential input signal to differential input currents;
- a bias voltage source;
- a first FET and a second FET;
- first and second current mirrors each mirroring one of said differential input currents to one of said first and said second FETs, said first current mirror comprising a third FET and a fourth FET having a common gate connection node, and said second current mirror comprising a fifth FET and a sixth FET having a common gate connection node;
- a third current mirror providing current to said first FET and to said second FET;
- a seventh FET sensing, at a gate thereof, a voltage on one of said first FET and said second FET, and having a source thereof connected to a voltage source;
- a current source providing a current to a drain of said seventh FET;
- and
- a capacitor having one plate connected to the common connection node for said current source and said seventh FET, and having another plate connected to the common gate connection node of one of said first current mirror and said second current mirror.
Dependencies are inferred from the claim text.