Power saving arrangement for a flash A/D converter
AssigneeLucent Technology Inc.
InventorG. N. Srinivasa Prasanna
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Abstract
An arrangement for reducing power consumption in a flash A/D converter uses a predictor module to compute the "next" digital output value (i.e., s(n+1)) and then uses this value to regulate the number of individual comparators required to perform an accurate conversion. The predictor module is disposed as a feedback element between the converter output and the comparator array. Based upon the prediction, the module transmits a control signal to the comparator array, turning "on" and "off" subsets of the comparators forming the array. By maintaining a large number of the comparators in the "off" state (usually, only half of the comparators need to be enabled), a significant power savings can be realized.
Claims7
An integrated circuit including a converter for converting an analog input signal into a digital output signal, comprising:
- a comparator array comprising a plurality of separate comparators, each comparator receiving in parallel the analog input signal as a first input and a reference signal as a second input signal and providing an output signal representative of the difference between the first and second input signals;
- decoding means responsive to the plurality of output signals from said comparator array for combining the plurality of output signals to form the digital output signal (s(n))
- CHARACTERIZED IN THAT the converter further comprises
- predictor means coupled between the output of the decoding means and the comparator array for predicting a subsequent digital output signal value (s(n+1)) and enabling only a subset of comparators of said comparator array in a predetermined window around said predicted value.
Dependencies are inferred from the claim text.