High speed interlaced analog interface

An apparatus for use in wide bandwidth analog to digital and digital to analog conversion, comprising:

• an input/output circuit for receiving and sending analog signals;
• a plurality of analog to digital converters, each having an input coupled to an output of said input/output circuit, wherein said plurality of analog to digital converters convert analog signals appearing at outputs of said plurality of analog to digital signals to digital signals;
• a digital to analog converter having an input and an output, said output of said digital to analog converter being coupled to said input/output circuit;
• and
• a digital signal processor having an interface for receiving and sending digital signals, said digital signal processor having an output coupled to said input of said digital to analog converter, said digital signal processor being responsive to said digital signals appearing at said outputs of said plurality of analog to digital converters, said digital signal processor including sum and multiplication means to apply offset and gain corrections to said digital signals and means for combining corrected digital signals at a single digital output.

A method for wide bandwidth analog to digital signal conversion comprising the steps of:

• receiving an analog signal;
• converting said analog signal to a plurality of digital signals;
• applying offset and gain correction parameters to each of said plurality of digital signals to form a plurality of corrected digital signals;
• and
• interleaving said plurality of corrected digital signals to form a single digital data signal.

A wide bandwidth analog to digital and digital to analog signal conversion apparatus to provide a two way interface between analog and digital domains, comprising:

• an input/output circuit for receiving and supplying analog signals, and for supplying analog reference voltages for calibration of the analog to digital conversion;
• a plurality of analog to digital converters coupled to said input/output circuit, said plurality of analog to digital converters being responsive to phased sampling control signals for converting said analog signals to corresponding digital data signals having an effective sampling rate substantially equal to a multiple of the rate for any one of said plurality of analog to digital converters;
• a digital signal processor coupled to receive said digital data signals, said digital signal processor for determining the appropriate correction parameters to correct offset and gain errors in the outputs of said plurality of analog to digital converters, applying the correction parameters to said digital data signals, interleaving the corrected digital data signals from said plurality of analog to digital converters to form a single digital data signal, filtering of the interleaved digital data signal to remove undesired conversion byproducts, supplying the filtered digital data stream to said digital domain, receiving digital signals to be converted to analog signals, and controlling the analog to digital and digital to analog conversion processes in response to control signals from said digital domain;
• and
• a digital to analog converter coupled to said digital signal processor and to said input/output circuit for converting digital data signals to analog signals.