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US 6,081,155 AGranted
Digital quadrature discriminator for demodulation of frequency-modulated information
AssigneeTexas Instruments Incorporated
InventorsGiridhar D. Mandyam, Eric Baissus
Life of this patent
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Abstract
A circuit is designed with a delay circuit (102) coupled to receive a frequency-modulated data signal (100) at a delay input terminal. The delay circuit produces the data signal (103) after a predetermined delay at a delay output terminal. An exclusive OR circuit (104) has a first input terminal coupled to the delay input terminal and has a second input terminal coupled to the delay output terminal.
Claims18
A circuit, comprising:
- a delay circuit coupled to receive a frequency-modulated data signal at a delay input terminal, the delay circuit producing the data signal after a predetermined delay at a delay output terminal;
- an exclusive OR circuit having an output terminal and having a first input terminal coupled to the delay input terminal and having a second input terminal coupled to the delay output terminal;
- a low pass filter having an output terminal and having an input terminal coupled to the exclusive OR circuit output terminal;
- and
- a sampling circuit having a first input terminal coupled to the low pass filter output terminal and having a second input terminal coupled to receive a clock signal, the sampling circuit producing an output signal having a frequency determined by the clock signal.
2 more elements
A discriminator circuit, comprising:
- a delay circuit coupled to receive a data signal at a delay input terminal, the delay circuit producing the data signal after a predetermined delay at a delay output terminal;
- and
- a digital logic circuit having an output terminal and having a first input terminal coupled to the delay input terminal and having a second input terminal coupled to the delay output terminal, the digital logic circuit producing a select signal at the output terminal;
- and
- a multiplex circuit coupled to receive the select signal, the multiplex circuit producing a first logic signal in response to a first logic state of the select signal, the multiplex circuit producing a second logic signal in response to a second logic state of the select signal.
2 more elements
A discriminator circuit, comprising:
- a delay circuit coupled to receive a data signal at a delay input terminal, the delay circuit producing the data signal after a predetermined delay at a delay output terminal;
- a digital logic circuit having an output terminal and having a first input terminal coupled to the delay input terminal and having a second input terminal coupled to the delay output terminal, the digital logic circuit producing a select signal at the output terminal;
- and
- a counter circuit coupled to receive the select signal, the counter circuit incrementing a counter output signal in response to a first logic state of the select signal, the counter circuit decrementing the counter output signal in response to a second logic state of the select signal.
1 more element
Dependencies are inferred from the claim text.