Multiple thread multiple data predictive coded parallel processing system and method

Abstract

A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses, and a series of processing units to access the buses and selectively execute the distributed instruction streams. The execution units each retrieve an instruction stream from an associated memory and place the instruction stream on a corresponding bus, while the processing units individually may select and execute any instruction stream placed on the corresponding buses. The processing units autonomously execute conditional instructions (e.g., IF/ENDIF instructions, conditional looping instructions, etc.), whereby an enable flag within the processing unit is utilized to indicate occurrence of conditions specified within a conditional instruction and control selective execution of instructions in response to occurrence of those conditions. An enable stack is utilized to facilitate processing and execution of nested conditional instructions by storing the states of the enable flag for each nested conditional instruction. The parallel processor may further delay placement of selected instruction streams onto corresponding buses until each processing unit selecting a particular instruction stream enters a state to execute that instruction stream. In addition, each execution unit may cease placing an instruction stream onto a corresponding bus in response to no processing units selecting that instruction stream for execution.

Dependencies are inferred from the claim text.