Circuit and method for multilevel signal decoding, descrambling, and error detection
AssigneeAdvanced Micro Devices, Inc.
InventorIan Crayford
Life of this patent
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Abstract
At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.
Claims17
A circuit for decoding a multilevel signal, comprising:
- a plurality of level detectors for comparing the multilevel signal to respective voltage levels and producing therefrom corresponding bit streams;
- a plurality of digital delay lines, coupled to outputs of respective level detectors, each digital delay line including a plurality of digital delay elements coupled in series for delaying a corresponding bit stream;
- and
- decoder logic coupled to outputs of at least selected elements of the each plurality of digital delay elements for receiving in parallel a plurality of bits from corresponding bit streams, and decoding the plurality of bits.
A multilevel decoder circuit comprising:
- a first level detector for comparing a multilevel signal to a prescribed positive level;
- a first digital delay line coupled to an output of said first level detector for delaying an output signal thereof;
- a second level detector for comparing the multilevel signal to a prescribed negative level;
- a second digital delay line coupled to an output of said second level detector for delaying an output signal thereof;
- and
- multilevel decode logic coupled to said first digital delay line and said second digital delay line and configured for outputting a plurality of decoded bits based on a first plurality of bits received from said first digital delay line and a second plurality of bits received from said second digital delay line.
A method of decoding a multilevel signal, comprising the steps of:
- comparing the multilevel signal to a plurality of levels to produce therefrom a plurality of bit streams;
- repeatedly delaying by a common delay period a plurality of bits from each bit stream;
- tapping the plurality of bits in parallel;
- and
- decoding the tapped plurality of bits to produce a plurality of decoded bits.
Dependencies are inferred from the claim text.