US 6,077,780 A · Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure

Abstract

A method for filling, with a conductive material, a high aspect ratio opening such as a via hole or a trench opening within an integrated circuit minimizes the formation of voids and seams. This conductive material such as copper which fills the high aspect ratio opening is amenable for fine line metallization. The method of the present invention includes steps for enhancing copper plating processes such as copper electroplating or copper electroless plating. This method includes a first step of copper plating for depositing a thin layer of copper within the integrated circuit opening. This thin layer preferably has a thickness on the field regions surrounding the opening that is less than 1/2 of the width of the opening. Then, copper reflow heats this thin deposited copper layer within the opening to minimize the occurrence of any seams within this copper layer. Finally, a second step of copper plating completely fills the integrated circuit opening. This two-step copper plating process with intermittent copper reflow minimizes formation of seams and subsequently minimizes eletromigration failure within filled integrated circuit openings having high aspect ratio.

Claims15

Dependent claims

A method for filling, with a conductive material, an opening having a width and a depth within an integrated circuit, said opening abutting a bottom metal line, the method comprising the steps of:

A. performing a first deposition of said conductive material by one of electroplating and electroless plating to partially fill the opening with the conductive material;
B. reflowing the conductive material filled within the opening by heating the conductive material filled within the opening, after said step A of performing said first deposition to partially fill the opening;
wherein said conductive material partially fills said opening after said step B of reflowing the conductive material within said opening;
and
C. performing a second deposition of said conductive material by one of electroplating and electroless plating to completely fill the opening with the conductive material, after said step B of reflowing the conductive material that partially fills the opening.

2 more elements

A method for filling, with copper, a via hole having a width and a depth within an integrated circuit, the via hole abutting a bottom level copper line, the method comprising the steps of:

A. depositing a barrier layer within the via hole to impede diffusion of copper within the via hole into insulating material surrounding the via hole, wherein the barrier layer is comprised of one of tantalum, tantalum nitride, tantalum copper, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium nitride, titanium/titanium nitride, and titanium silicon nitride;
B. depositing a wetting layer within the via hole, wherein the wetting layer has a thickness less than ten nanometers, and wherein the wetting layer is comprised of one of titanium, aluminum, silicon, magnesium, palladium, tin, cobalt, nickel, iron, chromium, zinc, cadmium, gold, beryllium, platinum, and manganese, copper tantalum and copper tungsten, and a copper-included alloy of one of titanium, aluminum, silicon, magnesium, palladium, tin, cobalt, nickel, iron, chromium, zinc, cadmium, gold, beryllium, platinum, and manganese;
C. depositing a seed layer of copper within the via hole, wherein the seed layer is deposited by one of chemical vapor deposition and physical vapor deposition;
D. performing a first deposition of copper by one of electroplating and electroless plating to partially fill the via hole with copper using an organic-free plating solution to reduce carbon impurities within the copper, wherein the copper filled within the via hole has a thickness on field regions surrounding the via hole that is less than 1/2 of the width of the via hole;
E. reflowing the copper within the via hole by heating the copper within the via hole, after said step D of performing said first deposition to partially fill the via hole;
wherein said copper partially fills said via hole after said step E of reflowing the copper within said via hole;
F. performing a second deposition of copper by one of electroplating and electroless plating to completely fill the via hole with copper, after said step E of reflowing the copper that partially fills the via hole;
and
G. polishing a surface of the integrated circuit having the filled via hole to remove excess copper deposited on field regions surrounding the via hole and to planarize the surface of the integrated circuit.

6 more elements

Dependencies are inferred from the claim text.

Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure

Life of this patent

Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure

Life of this patent

Abstract

Claims15