Method and apparatus to force a thread switch in a multithreaded processor

A method of computer processing, comprising:

• (a) setting a first time-out value;
• (b) loading a decrementer register when a thread switch occurs to a first thread;
• (c) executing the first thread of instructions in a multithreaded processor;
• (d) decrementing the decrementer register every period the first thread executes until the decrementer register reaches a first limit;
• (e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value
• (f) setting a second time-out value different from the first time-out value;
• (g) loading the decrementer register when a thread switch occurs to a second thread;
• (h) decrementing the decrementer every time period the second thread executes until the decrementer register reaches a second limit;
• (i) sending a second time-out signal to the thread switch controller when the second limit is equivalent to the second time-out value.

A method of computer processing, comprising:

• (a) loading a decrementer register when a thread switch occurs to a first thread;
• (b) setting a first time-out value less than five times longer than a most frequent longest latency event which inhibits the first thread from executing;
• (c) executing the first thread of instructions in a multithreaded processor;
• (d) decrementing the decrementer register every period the first thread executes until the decrementer register reaches a first limit;
• (e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value.

A computer processor, comprising:

• (a) a multithreaded processor capable of switching between at least two threads of instructions, at least one of the threads being an active thread executing instructions in the multithreaded processor;
• (b) a time-out counter which counts the number of cycles that the active thread executes;
• and
• (c) a time-out register operatively connected to the multithreaded processor and having a predetermined number which generates a time-out signal when the time-out counter equals the predetermined number in the time-out register and the active thread is unable to perform useful processing of instructions.

A computer system, comprising:

• (a) a multithreaded processor capable of switching processing between at least two threads of instructions when the multithreaded processor experiences one of a plurality of processor latency events;
• (b) a plurality of internal connections connecting the multithreaded processor to a plurality of memory elements wherein access to any of the plurality of memory elements by the multithreaded processor causes one of the plurality of processor latency events;
• (c) a plurality of external connections connecting the multithreaded processor to at least one external memory device, at least one external communication device, an external computer network, or at least one input/output device wherein access to any of the devices or the network by the multithreaded processor causes one of the plurality of processor latency events
• (d) at least one time-out counter which counts the number of cycles that each of the at least two threads of instructions executes;
• (e) at least one time-out register operatively connected to the multithreaded processor and having a predetermined number which generates a time-out signal when the at least one time-out counter equals the predetermined number in the at least one time-out register;
• (f) a thread switch controller which sends a switch signal to said multithreaded processor in response to the time-out signal and forces the multithreaded processor to switch to another of the at least two threads.

A computer processor, comprising:

• (a) means for processing a thread of instructions;
• (b) means for switching said thread of instructions into or out of said processing means;
• (c) means for counting a number of cycles that said processing means is processing;
• (d) means for storing a time-out value;
• and
• (e) means for generating a time-out signal when said number of cycles is equal to said time-out value and said thread of instructions is not performing useful processing when said thread is in said processing means.