Technique for reducing peak current in memory operation
AssigneeLSI Logic Corporation
InventorJeff S. Brown
Life of this patent
Estimating the term…
Abstract
A circuit in a memory device and a method for precharging at least one bit line in the memory device. The circuit includes a primary precharger and a secondary precharger in communication with the bit line. The secondary precharger gradually precharges the bit line before the primary precharger precharges the bit line between memory operations.
Claims18
A circuit in a memory device for precharging at least one bit line in the memory device, said circuit comprising:
- a primary precharger in communication with the bit line;
- and
- a secondary precharger in communication with the bit line, wherein said secondary precharger precharges the bit line before said primary precharger precharges the bit line between memory operations.
A circuit in a dynamic random access memory for precharging at least one bit line in the memory device, said circuit comprising:
- a primary precharger in communication with the bit line;
- a secondary precharger in communication with the bit line, wherein said secondary precharger gradually precharges the bit line before said primary precharger precharges the bit line between memory operations, wherein said secondary precharger includes at least one pullup device which is smaller than a pullup device of said primary precharger, and wherein said primary precharger and said secondary precharger are separate and independent from each other;
- a memory enable circuit connected to said primary precharger, wherein said primary precharger is configured to trigger off of an external enable signal which is received from said memory enable circuit;
- and
- a wordline connected to said secondary precharger, wherein said wordline de-asserts prior to completion of a memory access, wherein said secondary precharger is configured to enable and gradually precharge the bit line once the wordline enable de-asserts.
A method of precharging at least one bit line in a memory device, said method comprising:
- providing a primary precharger in communication with the bit line;
- providing a secondary precharger in communication with the bit line;
- and
- using said secondary precharger to precharge the bit line before using said primary precharger to precharge the bit line between memory operations.
A method of precharging at least one bit line in a memory device, said method comprising:
- providing a primary precharger in communication with the bit line;
- providing a secondary precharger in communication with the bit line, wherein said secondary precharger is separate and independent from said primary precharger;
- using said secondary precharger to gradually precharge the bit line before using said primary precharger to precharge the bit line between memory operations, wherein said secondary precharger includes at least one pullup device which is smaller than a pullup device of said primary precharger;
- providing a memory enable circuit connected to said primary precharger, wherein said primary precharger is configured to trigger off of an external enable signal which is received from said memory enable circuit;
- and
- providing a wordline connected to said secondary precharger, wherein said wordline de-asserts prior to completion of a memory access, wherein said secondary precharger is configured to enable and gradually precharge the bit line once the wordline enable de-asserts.
Dependencies are inferred from the claim text.