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US 6,075,413 AGranted
Amplifier circuit and control signal generator
AssigneeSony Corporation
InventorMasayuki Katakura
Life of this patent
Estimating the term…
Abstract
By providing differential resistors in common emitters of pairs of differential transistor and differentially taking out signals from collectors, a circuit excellent in low noise property and linearity was obtained. Further, a ring type voltage controlled oscillation circuit is provided comprising n number of stages of variable delay circuits, a control signal generation circuit weighting n+1 outputs taken out of the voltage controlled oscillation circuit by a phase control signal voltage and controlling the phase, and a phase locked loop means for locking the phase by comparing the output of the voltage controlled oscillation circuit and an external pixel clock.
Claims3
An input circuit, comprising:
- a pair of differential transistors provided with first and second transistors with emitters which are commonly connected and through which a collector current flows when there is no signal;
- a bias voltage source for biasing the base potential of each of the first and second transistors;
- an inputting means for differentially applying first and second input signal voltages superimposed on outputs of the bias voltage source to bases of the first and second transistors;
- an impedance circuit connected to the common emitters of the pair of differential transistors and provided with a differential resistor;
- and
- an outputting means for differentially obtaining output signals from the collector currents of the first and second transistors,
- wherein the product of the sum of collector currents of the first and second transistors when there is no signal and the differential resistor of the impedance circuit is set to a value of less than a thermoelectric voltage of the first and second transistors.
4 more elements
An input circuit, comprising:
- a pair of differential transistors provided with first and second transistors with emitters which are commonly connected and through which the collector current (IO) flows when there is no signal;
- a bias voltage source for biasing the base potential of each of the first and second transistors;
- an inputting means for differentially applying first and second input signal voltages superimposed on outputs of the bias voltage source to bases of the first and second transistors;
- an impedance circuit connected to the common emitters of the pair of differential transistors and provided with a differential resistor;
- a third transistor with an emitter which is connected to the common emitters of the first and second transistors via a resistor element and through which a collector current (Ix) flows when there is no signal;
- a second bias voltage source for biasing the base potential of the third transistor;
- and
- an outputting means for differentially obtaining output signals from the collector currents of the first and second transistors,
- wherein the product of the sum (2.times.Io+Ix) of the collector currents of the first and second transistors when there is no signal and the collector current of the third transistor when there is no signal and the differential resistor of the impedance circuit is set to a value of at least 1/2 and not more than 10 times of the thermoelectric voltage of the first and second transistors.
6 more elements
An input circuit, comprising:
- a pair of differential transistors provided with first and second transistors with emitters which are commonly connected and through which a collector current (Io) flows when there is no signal;
- a bias voltage source for biasing the base potential of each of the first and second transistors;
- an inputting means for differentially applying first and second input signal voltages superimposed on outputs of the bias voltage source to bases of the first and second transistors;
- an impedance circuit connected to the common emitters of the pair of differential transistors and provided with a differential resistor;
- a third transistor with an emitter which is connected to the common emitters of the first and second transistors and through which a collector current (Ix) flows when there is no signal;
- a second bias voltage source for biasing the base potential of the third transistor;
- and
- an outputting means for differentially obtaining output signals from the collector currents of the first and second transistors,
- wherein the product of the sum (2.times.Io+Ix) of the collector currents of the first and second transistors when there is no signal and the collector current of the third transistor when there is no signal and the differential resistor of the impedance circuit is set to a value of at least 1/2 and not more than 10 times the thermoelectric voltage of the first and second transistors.
6 more elements
Dependencies are inferred from the claim text.