Selectively accessing test access ports in a multiple test access port environment

A method of using a plurality of test interfaces, which are coupled between a test bus and respective target circuits, to provide access to a register, comprising:

• A. receiving register select signals from the respective test interfaces;
• B. responding to a first of the register select signals, including selecting the register to perform a data transfer operation with the test bus;
• and
• C. responding to a second of the register select signals, including selecting the register to perform a data transfer operation with the test bus.

An electrical circuit, comprising:

• A. a test bus;
• B. a plurality of target circuits;
• and
• C. a plurality of test interfaces coupled to said test bus to provide for the test bus interfaces to communicate with said test bus simultaneously, each test interface is also coupled to a respective target circuit, each said test interface including a select output indicative of when said test interface is selected for communication with said test bus, and an enable input indicative of when said test interface is enabled for communication with said test bus and also indicative of when said test interface is disabled from communication with said test bus.

A method of controlling a plurality of test interfaces, the test interface coupled to a test bus to permit the test interfaces to communicate with the test bus simultaneously, the test interfaces also coupled to respective target circuits, comprising:

• A. indicating from a first of the test interfaces that the first test interface is selected for communication with the test bus;
• B. indicating to the first of the test interfaces that the first test interface is enabled for communication with the test bus;
• and
• C. indicating to a second of the test interfaces that the second interface is disabled from communication with the test bus.

An integrated circuit comprising:

• A. a test bus of leads including a test data input lead, a bus test data output lead, a test clock lead and a test mode select lead;
• B. boundary scan register circuits;
• C. plural circuit modules;
• D. a separate test access port connected to each of the boundary scan register circuits and the plural circuit modules, each test access port being connected to the test data input lead, the test clock lead and the test mode select lead and having a port test data output lead selectively coupled to the bus test data output lead, each test access port including a select output lead carrying a select signal indicating the selection of that test access port and including an enable input lead carrying an enable signal indicating that the test access port is enabled to communicate with the test data output lead;
• and
• E. selection circuits having an output connected to the bus test data output lead and having plural inputs connected to the port test data output leads;
• and
• F. a test access port linking module connected to the test data input lead, the test clock lead and the test mode select lead and having a module test data output lead selectively coupled to the bus test data output lead through the selection circuits, the linking module being connected to all of the select outputs and enable inputs and producing an enable signal in response to receiving at least a select signal.