Method for simultaneously fabricating a DRAM capacitor and metal interconnections

A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate, said substrate comprising a cell array and a periphery area, said method comprising:

• forming a first dielectric layer over said cell array area and said periphery;
• planarizing said first dielectric layer;
• simultaneously forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell, wherein a storage node contact hole of said plurality of first contact holes has a depth different from that of an interconnect contact hole of said plurality of first contact holes;
• forming a first conductive layer in said plurality of first contact holes and on said fist dielectric layer;
• patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously;
• forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections;
• and
• patterning said second dielectric layer and said second conductive layer to form a storage means in said cell array area, a first contact plug, a second contact plug, and a third contact plug in said periphery area, said first contact plug being electrically coupled to said bitline, said second contact plug being electrically coupled to said word line, and said third contact plug being electrically coupled to said substrate of said periphery area.