US 6,070,227 A · Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization

Abstract

A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits. The present invention greatly improves the page hit rate of computer systems, while requiring few additional resources.

Claims18

Dependent claims

A computer system comprising:

a processor that generates a logical address to facilitate memory accesses;
a main memory unit that includes a plurality of banks, wherein each bank of the plurality of banks includes a page buffer, and the main memory unit is addressed via bank, row and column bits;
a cache memory coupled to the processor, the cache memory holding a subset of contents of the main memory unit, wherein the cache memory is organized into sets of cache lines that are addressed by an index portion of the logical address, and a tag portion of the logical address is associated with each cache line;
a memory controller coupled between the main memory unit and the cache memory, wherein the memory controller generates from the logical address the bank, row, and column bits required by the main memory unit, and one or more bits from the tag portion of the logical address are used to generate a first set of one or more bank bits, thereby increasing the probability that a cache line cast out and a corresponding cache line read to the same cache line as the cache line cast out access different page buffers of the main memory unit.

1 more element

Dependencies are inferred from the claim text.

Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization

Life of this patent

Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization

Life of this patent

Abstract

Claims18