Receiver for a navigation system, in particular a satellite navigation system

A satellite navigation system receiver comprising at least two antennas, one of which is a reference antenna, a multiplexer for multiplexing signals from the antennas;

• a first processor operatively associated with said multiplexer to deliver at least one signal representative of a navigation parameter on the basis of signals from the multiplexer, the first processor including a first RF/IF converter operatively associated with the multiplexer and a first analog-to-digital converter;
• a second processor having an input that receives signals continuously from the reference antenna to deliver at least one reference signal representative of a parameter concerning the position of the reference antenna, the second processor including a second RF/IF converter operatively associated with the reference antenna and a second analog-to-digital converter;
• a frequency synthesizer common to the first and second processors and producing a local oscillator signal and a clock signal which are applied respectively firstly to at least the first and second RF/IF converters and to at least the first and second analog-to-digital converters;
• and processor means for processing the signals from the multiplexer and said at least one reference signal and for calculating at least one item of navigation data, wherein for each satellite signal to be processed, the receiver includes a processor block including a reference section forming a portion of the second processor and a slave section forming a portion of the first processor, each said section comprising:
• a baseband converter for converting into baseband and also for image frequency rejection;
• a numerically-controlled carrier oscillator having an output connected to an input of the baseband converter;
• a numerically-controlled code oscillator;
• a code generator controlled by said numerically-controlled code oscillator and generating early, punctual, and late codes E, P, and L;
• a correlator receiving the signal output in baseband from the baseband converter and the early, punctual, and late codes E, P, and L, as generated by the code generator, and outputting correlation signals;
• and
• an accumulator receiving the correlation signals as inputs and generating early, punctual, and late loop control signals as outputs;
• the input of the slave section baseband converter is connected to the output of the first analog-to-digital converter;
• the input of the reference section baseband converter is connected to the output of the second analog-to-digital converter;
• and
• the processor means includes a digital processor receiving the loop control signals generated by the accumulator of the reference section and by the accumulator of the slave section, and generating loop signals for the carrier oscillators and for the code oscillators of the reference section and of the slave section.

A satellite navigation system receiver comprising at least two antennas, one of which is a reference antenna;

• a multiplexer for multiplexing signals from the antennas;
• a first processor operatively associated with said multiplexer to deliver at least one signal representative of a navigation parameter on the basis of signals from the multiplexer, the first processor including a first RF/IF converter operatively associated with the multiplexer and a first analog-to-digital converter;
• a second processor having an input that receives signals continuously from the reference antenna to deliver at least one reference signal representative of a parameter concerning the position of the reference antenna, the second processor including a second RF/IF converter operatively associated with the reference antenna and a second analog-to-digital converter;
• a frequency synthesizer common to the first and second processors and producing a local oscillator signal and a clock signal which are applied respectively firstly to at least the first and second RF/IF converters and to at least the first and second analog-to-digital converters;
• and processor means for processing the signals from the multiplexer and said at least one reference signal and for calculating at least one item of navigation data, wherein, for each satellite signal to be processed, the receiver includes a processor block including a reference section forming a portion of the second processor, a slave section forming a portion of the first processor, and a section common to the first and second processors, wherein said common section includes:
• a numerically-controlled carrier oscillator having an output;
• a numerically-controlled code oscillator;
• and
• a code generator controlled by said numerically-controlled code oscillator and generating early, punctual, and late codes E, P, and L;
• wherein said reference section includes:
• a baseband converter for conversion into baseband and for image frequency rejection, said baseband converter having an input connected to the output of the second analog-to-digital converter and an input connected to the output of the numerically-controlled carrier oscillator;
• a correlator receiving the signal output in baseband from the baseband converter together with the early, punctual, and late codes E, P, and L generated by the code generator and outputting correlation signals;
• and
• an accumulator receiving the correlation signals as inputs and generating as outputs early, punctual, and late loop control signals;
• wherein said slave section includes:
• a baseband converter performing baseband conversion and image frequency rejection, said baseband converter having an input connected to the output of the first analog-to-digital converter, and an input connected to the output of the numerically-controlled carrier oscillator;
• a correlator receiving the signal output in baseband from the baseband converter together with the punctual code P generated by the code generator of the reference section, and outputting a punctual correlation signal;
• and
• an accumulator receiving the punctual correlation signal as its input and outputting a punctual loop control signal;
• and wherein the processor means includes a digital processor receiving the loop control signals generated by the accumulators of the reference section and of the slave section, and generating loop signals for the carrier oscillator and for the code oscillator.