Adjustable output driver circuit having parallel pull-up and pull-down elements
AssigneeMicron Technnology, Inc.
InventorBrent Keeth
Life of this patent
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Abstract
An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.
Claims20
An output driver circuit, comprising:
- a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal;
- a control circuit coupled to each of the control terminals of the active load devices of the first plurality of active load devices for sequentially activating or deactivating the active load devices in response to a first input signal received by the control circuit, the control circuit having a first inverter having an output coupled to the control terminal of one of the first plurality of active load devices, a second inverter having an output coupled to an input of the first inverter;
- and
- forcing circuitry coupled to the first and second inverters to couple the output of the second inverter to either the first voltage terminal or a second voltage terminal based upon an input of the second inverter and an output of the first inverter.
An output driver circuit, comprising:
- a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal;
- a second plurality of active load devices electrically coupled between the output node and a second voltage terminal, each active load device having a control terminal;
- a control circuit coupled to the control terminals of the first and second pluralities of active load devices for sequentially activating and deactivating the active load devices of the first and second pluralities in response to an input signal, the control circuit having a first plurality of inverters, each inverter having an output coupled to a respective control terminal of the active load devices of the first and second pluralities of active load devices, and a second plurality of inverters, each inverter having an output coupled to an input of a respective one of the first plurality of inverters;
- and
- forcing circuitry coupled to the first and second plurality of inverters for selectively coupling the output of the second inverters to either the first voltage terminal or the second voltage terminal.
A method for producing an output signal having a variable slew rate in response to an input signal, comprising:
- generating a first sequence of activation signals in response to the input signal, the first sequence of activation signals having an increasing delay with respect to the input signal;
- feeding forward the input signal and feeding back a respective one of the first sequence of activation signals to a forcing circuit;
- and
- applying each of the activation signals of the first sequence of activation signals to a respective control terminal of a first plurality of active load devices coupled between a first voltage terminal and an output node to sequentially activate or deactivate the first plurality of active load devices.
Dependencies are inferred from the claim text.