Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories

An interface apparatus, comprising:

• a processor;
• a first bus interface for receiving data from and transmitting data to a first data bus;
• a second bus interface for receiving data from and transmitting data to a second data bus;
• a triple port memory having first, second, and third ports for storing data into a plurality of storage cells and for reading stored data from the storage cells without allocation of access between the ports and the plurality of data storage cells;
• the first port being coupled to the first bus interface such that data received from the first data bus is stored in the storage cells and data read from the storage cells by the first bus interface is transmitted to the first data bus;
• the second port being coupled to the second bus interface such that data received from the second data bus is stored in the storage cells and data read from the storage cells by the second bus interface is transmitted to the second data bus;
• the processor being coupled to the third port for reading, processing, and storing data in the storage cells;
• and
• wherein the data stored to a particular storage cell through a particular port is available to be asynchronously read by another port independently of the particular port while the particular port is reading data from or storing data to another storage cell.

An interface apparatus, comprising:

• a multi-port memory having a at least four independent bi-directional data ports;
• a plurality of bus interfaces, each interface being connected to one of a separate data port of the at least four independent data ports for storing data in and reading data from the multi-port memory;
• and
• a plurality of data processors, each data processor being connected to a separate data port of the at least four independent data ports for simultaneously reading data from different portions of the multi-port memory, processing the stored data, and storing the processed data in the multi-port memory without allocation of access by the at least four independent data ports to the multi-port memory during reading data from and storing data to the multi-port memory.

A method for interfacing data, comprising:

• providing a multi-port memory having a plurality of data storage cells;
• storing data received through a first port from a first data bus into a first portion of the plurality of storage cells;
• processing, through a second port, the data stored in the first portion of the plurality of data storage cells while independently and simultaneously storing data being received through the first port from the first data bus into a second portion of the plurality of storage cells;
• and
• reading, through a third data port, processed data stored in the first portion of the plurality of data storage cells while independently and simultaneously processing, through the second port, the data stored in the second portion of the plurality of data storage cells and while independently and simultaneously storing data being received through the first port from the first data bus into a third portion of the plurality of storage cells.

An interface apparatus, comprising:

• a multi-port memory having a plurality of data storage cells and having at least three independent bi-directional data ports that are configured to simultaneously and independently write data to and read data from the plurality of data storage cells without allocation of access between the data ports and the plurality of data storage cells;
• first means for coupling a first port of the bi-directional data ports to a first bi-directional data bus;
• second means for coupling a second port of the bi-directional data ports to a second bi-directional data bus;
• and
• a processor coupled to a third port of the bi-directional data ports for operating on data in the plurality of data storage cells.