US 6,067,262 A · Redundancy analysis for embedded memories with built-in self test and built-in self repair

Abstract

An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

Claims22

Dependent claims

A method for testing integrated circuits having built-in self test and built-in self repair circuitry, comprising the steps of:

applying a first stress factor to an integrated circuit die;
performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die;
generating first fault information pertaining to any faults detected by the first built-in self test analysis;
applying a second stress factor to the integrated circuit die;
performing a second built-in self test analysis on the predetermined portion of the integrated circuit die;
generating second fault information pertaining to any faults detected by the second built-in self test analysis;
and
comparing the first fault information with the second fault information to ascertain any differences.

5 more elements

A method for testing integrated circuits with embedded memories and built-in self test and built-in self repair circuitry, comprising the steps of:

applying a first stress factor to an integrated circuit die;
performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die;
generating first fault information pertaining to any faults detected by the first built-in self test analysis;
applying a second stress factor to the integrated circuit die;
performing a second built-in self test analysis on the predetermined portion of the integrated circuit die;
generating second fault information pertaining to any faults detected by the second built-in self test analysis;
applying at least one additional stress factor;
performing at least one additional built-in self test analysis on the predetermined portion of the integrated circuit die;
generating at least one additional fault information pertaining to any faults detected by the additional built-in test analysis;
and
comparing the first fault information, the second fault information and the at least one additional fault information to ascertain any differences.

8 more elements

Dependencies are inferred from the claim text.

Redundancy analysis for embedded memories with built-in self test and built-in self repair

Life of this patent

Redundancy analysis for embedded memories with built-in self test and built-in self repair

Life of this patent

Abstract

Claims22