Method for fabricating a shielded multilevel integrated circuit capacitor
AssigneeTritech Microelectronics, Ltd.
InventorDavid Ho Seng Poh
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AssigneeTritech Microelectronics, Ltd.
InventorDavid Ho Seng Poh
Estimating the term…
A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit. The first plate and the third plate are connected to give a total capacitance given by the sum of capacitances between the first plate and second plate and between the second plate and third plate.
A method for fabricating a capacitor structure on a surface of a semiconductor substrate having a first conductivity type, comprising the steps of:
Dependencies are inferred from the claim text.