Multi-speed DSP kernel and clock mechanism

A method for controlling the processing rate of a processor within a computing device, wherein said method comprises steps of:

• a) executing a test sequence to determine, for each function which can be performed by said processor, a maximum processing speed, within a plurality of processing speeds at which said processor can be operated, at which said function can be reliably performed by said processor, and writing said maximum processing speed within a processing speed table, wherein said test sequence includes operating various of said functions at various of said processing speeds by said processor to determine reliability of operation;
• b) determining for a task scheduled to be performed by said processor, the functions to be performed by said processor, and by comparison to said processing speed table, a maximum operating speed at which all said functions to be performed during said task may be performed reliably thereby;
• c) performing said task at said maximum operating speed;
• and
• d) returning to step b) when another task is scheduled to be performed by said processor;
• and
• wherein step a) includes steps of:
• e) resetting a first counter, with said first counter indicating a function which can be performed by said processor;
• f) resetting a second counter, with said second counter indicating a processing speed within said plurality thereof;
• g) operating said processor to perform a function indicated by said first counter at a processing speed indicated by said second counter;
• h) determining if a failure has occurred during operation of said processor in step g);
• i) if a failure has not occurred, as determined in step h), determining if a maximum value of said second counter has been reached;
• j) if a maximum value of said second counter has not been reached, as determined in step l), incrementing said second counter and returning to step g)
• k) if a maximum value of said second counter has been reached, as determined in step l), writing said maximum value in said processing speed table in a location corresponding to a function indicated by said first counter, and determining if a maximum value of said first counter has been reached;
• l) if a maximum value of said first counter has been reached, as determined in step k), ending step a)
• m) if a maximum value of said first counter has not been reached, as determined in step k) incrementing said first counter and returning to step f);
• n) if a failure has occurred, as determined in step h) decrementing said second counter, writing a value of said second counter in said processing speed table in a location corresponding to said function indicated by said first counter and determining if said first counter has reached a maximum value;
• o) if a maximum value of said first counter has been reached, as determined in step n), ending step a);
• and
• p) if a maximum value of said first counter has not been reached, as determined in step n) incrementing said first counter and returning to step f).