Matrix for switching between two multiplex groups

A matrix for switching between an input group and an output group of at least two time-division multiplexes including:

• a first, second and third buffer for storing data arriving in multiplex at input junctions to issue these data in multiplex on output junctions according to an assignment, by an assignment memory, of each time slot of an input multiplex to a time slot of an output multiplex, the first buffer being provided for receiving the data relative to transmissions as they are issued by a series-to-parallel converter receiving the input junctions and for enabling, at least when the data belong to a transmission channel including a plurality of time slots of a same multiplex, to selectively transfer data stored in the first buffer to the second or third buffer;
• two counters which, with the assignment memory, provide in a timely manner read and write addresses for the first, second and third buffers such that signals output to the plurality of output multiplexes are in proper time sequence, wherein one of the counters in addition selects to which of the second or third buffers data stored in the first buffer gets transferred;
• including means for verifying that a bidirectional link between two subscribers through another switch matrix located on the path of the transmission between the two subscribers has been established;
• and
• wherein said verifying means comprise a generator of a pseudo-random sequence and an analyzer of this pseudo-random sequence, the pseudo-random sequence being generated by a shift register associated with the generator.

A matrix for switching between an input group and an output group of at least two time-division multiplexes, including:

• a first, second and third buffer for storing data arriving in multiplex at input junctions to issue these data in multiplex on output junctions according to an assignment of each time slot of an input multiplex to a time slot of an output multiplex, the first buffer being provided for receiving the data relative to transmissions as they are issued by a series-to-parallel converter receiving the input junctions and for enabling, at least when the data belong to a transmission channel including a plurality of time slots of a same multiplex, to selectively transfer data stored in the first buffer to the second or third buffer;
• an assignment memory, programmable by a microprocessor and which stores, for each outgoing time slot to be sent to one of the output junctions via a parallel-to-series converter, in addition to an address of an incoming time slot associated therewith and which is stored at an address of an outgoing time slot, an additional bit, a state of which differentiates a transmission channel including a single time slot from a transmission channel including a plurality of time slots of a same multiplex, wherein a data word associated with a transmission channel including a single time slot per multiplex frame is read, from the first buffer, at an address issued by the assignment memory to be directly sent to the parallel-to-series converter;
• two counters which, with the assignment memory, provide in a timely manner read and write addresses for the first, second and third buffers such that signals output to the plurality of output multiplexes are in proper time sequence;
• and
• wherein each of the buffers is constituted by a distinct memory, the address for reading from the first buffer and for writing into one of the two other buffers being, at least for transmission channels including several time slots of a same multiplex, issued by the second counter, the address for reading from the other of the two buffers being then issued by the assignment memory.