Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits

A method for forming a semiconductor structure, the method comprising the steps of:

• providing a substrate having a surface;
• forming a dielectric layer over the substrate using a chemical vapor deposition (CVD), wherein a the CVD process causes a formation of bulk traps and interface traps;
• forming a gate layer over the dielectric layer;
• etching the gate layer and the dielectric layer in a plasma environment to form a gate region, wherein the plasma environment at least partially causes a first leakage current between the gate and the substrate;
• and
• performing a low temperature wet oxidation to reduce the bulk traps and interface traps, wherein there is a second leakage current between the gate and substrate following the step of performing a low temperature wet oxidation and the second leakage current is less than the first leakage current.

A method for forming a semiconductor structure, the method comprising the steps of:

• forming a dielectric layer having an oxide equivalent thickness of less than approximately 40 Angstroms over a semiconductor substrate;
• forming a gate layer;
• etching the gate layer and the dielectric layer, by a plasma etch process, to form a patterned gate structure;
• placing the semiconductor substrate in an oxidation chamber;
• heating the oxidation chamber to approximately 750.degree. to 850.degree. Celsius;
• introducing oxygen into the oxidation chamber;
• introducing a diluted amount of hydrogen into the oxidation chamber at a substantially same time as the oxygen;
• and
• maintaining 750.degree. to 850.degree. Celsius in the oxidation chamber for approximately 15 minutes.