Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair

A system comprising:

• a bus;
• a first and second agent coupled to said bus, said first agent including a first plurality of inputs coupled to said bus and said second agent including a second plurality of inputs coupled to said bus;
• a first circuit included in said first agent to determine a first internal agent identifier;
• a second circuit included in said second agent to determine a second internal agent identifier;
• initialization logic coupled to said bus to,
• issue a first signal to one input of said first plurality of inputs and one input of said second plurality of inputs over said bus at a predetermined condition indicating to said first agent and said second agent whether said system is operating in a first mode or a second mode, and
• issue a second signal to one of said first plurality of inputs and one of said second plurality of inputs over said bus at said predetermined condition;
• a third circuit included in said first agent to determine said first agent's relationship with said second agent based on said second signal;
• and
• a fourth circuit included in said second agent to determine said second agent's relationship with said first agent based on said second signal.

A system comprising:

• a bus;
• and
• one or more bus agents coupled to said bus wherein each of said one or more bus agents includes,
• a plurality of inputs,
• a circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at a predetermined condition, whether said bus agent is operating in an independent mode or a master/checker mode, and
• a reconfigurable signal path coupled to both said plurality of inputs and a plurality of internal signals, wherein said reconfigurable signal path is to connect a signal received on a second input of said plurality of inputs to a first internal signal of said plurality of internal signals responsive to said first signal being received in a first state, and to connect said signal received on said second input to a second internal signal of said plurality of internal signals responsive to said first signal being received in a second state.

An apparatus comprising:

• a plurality of inputs;
• a first circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at system reset, whether said apparatus is operating in an independent mode or a master/checker mode;
• and
• a second circuit, coupled to said plurality of inputs, to prevent a second signal to be issued by said apparatus from being driven onto a bus coupled to said apparatus.

A method for initializing a plurality of agents in a computer system to operate in either an independent mode or a master/checker mode in which each agent is coupled to a bus over a plurality of inputs, said method comprising the steps of:

• issuing a first signal to one input of said plurality of inputs of each agent of said plurality of agents over said bus at a predetermined condition indicating to said plurality of agents whether said system is operating in said independent mode or said master/checker mode;
• issuing a second signal to one input of said plurality of inputs of each agent of said plurality of agents over said bus at said predetermined condition;
• each agent of said plurality of agents determining an internal agent identification based on the identity of said one input on which said second signal was received;
• and
• each agent of said plurality of agents determining its relationship with the remaining agents of said plurality of agents based on whether said first signal is in a first state or a second state.

An apparatus comprising:

• a plurality of inputs;
• a circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at a predetermined condition, whether said apparatus is operating in an independent mode or a master/checker mode;
• and
• a reconfigurable signal path coupled to both said plurality of inputs and a plurality of internal signals, wherein said reconfigurable signal path is to connect a signal received on a second input of said plurality of inputs to a first internal signal of said plurality of internal signals responsive to said first signal being received in a first state, and to connect said signal received on said second input to a second internal signal of said plurality of internal signals responsive to said first signal being received in a second state.

A system comprising:

• a bus;
• a plurality of bus agents coupled to said bus wherein each said bus agent includes an internal agent identifier and a plurality of inputs coupled to said bus, wherein a first bus agent of the plurality of bus agents comprises a digital signal processor;
• a first processor being one of said plurality of bus agents and including a circuit to determine said internal agent identifier for said first processor;
• and
• initialization logic to,
• issue a first signal to one of said plurality of inputs over said bus at a predetermined condition indicating to said first processor whether said system is operating in a multiple processor mode or a master/checker mode, and
• issue a second signal to one of said plurality of inputs over said bus at said predetermined condition, wherein said first processor determines said internal agent identifier based on said first and second signals.

A system comprising:

• a first bus;
• a plurality of processors coupled to said first bus wherein each said processor includes an internal agent identifier and a plurality of inputs coupled to said first bus;
• a second bus coupled to said first bus via a bridge;
• a storage device controller, coupled to said second bus, to control data transfers to and from a removable magnetic storage device;
• a first processor being one of said plurality of processors and including a circuit to determine said internal agent identifier for said first processor;
• and
• initialization logic to,
• issue a first signal to one of said plurality of inputs over said first bus at a predetermined condition indicating to said first processor whether said system is operating in a multiple processor mode or a master/checker mode, and
• issue a second signal to one of said plurality of inputs over said first bus at said predetermined condition, wherein said processor determines said internal agent identifier based on said first and second signals.

A system comprising:

• a bus;
• a digital signal processor coupled to said bus;
• and
• a first processor, coupled to said bus, including,
• a plurality of inputs,
• a circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at a predetermined condition, whether said first processor is operating in an independent mode or a master/checker mode, and
• a reconfigurable signal path coupled to both said plurality of inputs and a plurality of internal signals, wherein said reconfigurable signal path is to connect a signal received on a second input of said plurality of inputs to a first internal signal of said plurality of internal signals responsive to said first signal being received in a first state, and to connect said signal received on said second input to a second internal signal of said plurality of internal signals responsive to said first signal being received in a second state.

A system comprising:

• a first bus;
• a second bus coupled to said first bus via a bridge;
• a storage device controller, coupled to said second bus, to control data transfers to and from a removable magnetic storage device;
• and
• a plurality of processors coupled to said first bus wherein each of said plurality of processors includes,
• a plurality of inputs,
• a circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at a predetermined condition, whether said processor is operating in an independent mode or a master/checker mode, and
• a reconfigurable signal path coupled to both said plurality of inputs and a plurality of internal signals, wherein said reconfigurable signal path is to connect a signal received on a second input of said plurality of inputs to a first internal signal of said plurality of internal signals responsive to said first signal being received in a first state, and to connect said signal received on said second input to a second internal signal of said plurality of internal signals responsive to said first signal being received in a second state.

A system comprising:

• a bus;
• a digital signal processor coupled to said bus;
• a plurality of processors coupled to said bus, wherein each of the plurality of processors includes,
• a plurality of inputs,
• a first circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at system reset, whether said processor is operating in an independent mode or a master/checker mode, and
• a second circuit, coupled to said plurality of inputs, to prevent a second signal to be issued by said processor from being driven onto said bus.

A system comprising:

• a bus;
• a storage device controller, coupled to said bus, to control data transfers to and from a removable magnetic storage device;
• and
• a processor, coupled to the bus, including,
• a plurality of inputs,
• a first circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at system reset, whether said processor is operating in an independent mode or a master/checker mode, and
• a second circuit, coupled to said plurality of inputs, to prevent a second signal to be issued by said processor from being driven onto said bus.

A system comprising:

• a bus;
• digital signal processor coupled to said bus;
• a processor, coupled to said bus, including,
• a plurality of inputs,
• a first circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at system reset, whether said processor is operating in an independent mode or a master/checker mode, and
• a second circuit, coupled to said plurality of inputs, to prevent a second signal to be issued by said processor from being driven onto said bus.

A system comprising:

• a bus;
• a digital signal processor coupled to said bus;
• and
• a processor, coupled to said bus, including,
• a plurality of inputs,
• a circuit, coupled to a first input of said plurality of inputs, to determine, based on a first signal received on said first input at a predetermined condition, whether said processor is operating in an independent mode or a master/checker mode, and
• switchover logic coupled to said plurality of inputs for feeding a signal received on a second input of said plurality of inputs along a first signal path responsive to said first signal being received in a first state, and for feeding said signal received on said second input along a second signal path responsive to said first signal being received in a second state.