Secure processor with external memory using block chaining and block re-ordering

An apparatus for communicating program information, comprising:

• a secure circuit for providing said program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• and
• a first communication path which is adapted to communicate a group of blocks of said program information from said secure circuit to the external storage device in a first block chain;
• wherein:
• units of said program information are communicated from said secure circuit to the external storage device using randomly varying sequences.

A method for processing program information, comprising the steps of:

• storing at least one block of the program information in a secure circuit that includes a central processing unit (CPU) and at least one block buffer;
• storing the program information external to said secure circuit in an external storage device;
• communicating a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain via a first communication path;
• and
• communicating the program information from the at least one block buffer to the CPU for processing therein via a second communication path;
• wherein:
• the first block chain comprises authentication data derived from the group of blocks of program information;
• and
• said secure circuit comprises an authentication circuit that is responsive to said at least one block buffer for processing the first block chain to verify the authentication data thereof prior to the program information being communicated to the CPU.

An apparatus for processing program information, comprising:

• a secure circuit including a central processing unit (CPU) and at least one block buffer for storing at least one block of the program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• a first communication path which is adapted to communicate a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain;
• and
• a second communication path which is adapted to communicate the program information from the at least one block buffer to the CPU for processing therein;
• wherein:
• units of said program information are communicated from the external storage device to said at least one block buffer using randomly varying sequences.

An apparatus for processing program information, comprising:

• a secure circuit including a central processing unit (CPU) and at least one block buffer for storing at least one block of the program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• a first communication path which is adapted to communicate a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain;
• and
• a second communication path which is adapted to communicate the program information from the at least one block buffer to the CPU for processing therein;
• wherein:
• a plurality of units of program information is communicated from the external storage device to said secure circuit in units of varying length;
• and
• the length of each unit is determined according to a processing latency of the associated program information of the respective units.

An apparatus for processing program information, comprising:

• a secure circuit including a central processing unit (CPU) and at least one block buffer for storing at least one block of the program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• a first communication path which is adapted to communicate a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain;
• a second communication path which is adapted to communicate the program information from the at least one block buffer to the CPU for processing therein;
• a third communication path which is adapted to communicate a group of blocks of program information from said secure circuit to said external storage device in a second block chain;
• and
• a length determination circuit for randomly varying the length of units of the program information for the second block chain.

An apparatus for processing program information, comprising:

• a secure circuit including a central processing unit (CPU) and at least one block buffer for storing at least one block of the program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• a first communication path which is adapted to communicate a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain;
• and
• a second communication path which is adapted to communicate the program information from the at least one block buffer to the CPU for processing therein;
• wherein:
• said program information comprises a plurality of strings of instructions which are to be executed by said CPU in a first sequence;
• said secure circuit includes a re-ordering means;
• in said first block chain, the strings of instructions are provided in a second sequence that differs from the first sequence;
• and
• said re-ordering means are associated with the at least one block buffer for re-ordering the strings of instructions to the first sequence.

An apparatus for communicating program information, comprising:

• a secure circuit for providing said program information;
• an external storage device which is adapted to store the program information external to said secure circuit;
• and
• a first communication path which is adapted to communicate a group of blocks of said program information from said secure circuit to the external storage device in a first block chain;
• wherein a plurality of chains of program information are communicated from said secure circuit to the external storage device in a randomly varying sequence.

A method for processing program information, comprising the steps of:

• storing at least one block of the program information in a secure circuit that includes a central processing unit (CPU) and at least one block buffer;
• storing the program information external to said secure circuit in an external storage device;
• communicating a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain via a first communication path;
• and
• communicating the program information from the at least one block buffer to the CPU for processing therein via a second communication path;
• wherein:
• units of said program information are communicated from the external storage device to said at least one block buffer using randomly varying sequences.

A method for processing program information, comprising the steps of:

• storing at least one block of the program information in a secure circuit that includes a central processing unit (CPU) and at least one block buffer;
• storing the program information external to said secure circuit in an external storage device;
• communicating a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain via a first communication path;
• and
• communicating the program information from the at least one block buffer to the CPU for processing therein via a second communication path;
• wherein:
• a plurality of units of program information is communicated from the external storage device to said secure circuit in units of varying length;
• and
• the length of each unit is determined according to a processing latency of the associated program information of the respective units.

A method for processing program information, comprising the steps of:

• storing at least one block of the program information in a secure circuit that includes a central processing unit (CPU) and at least one block buffer;
• storing the program information external to said secure circuit in an external storage device;
• communicating a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain via a first communication path;
• and
• communicating the program information from the at least one block buffer to the CPU for processing therein via a second communication path;
• communicating a group of blocks of program information from said secure circuit to said external storage device in a second block chain via a third communication path;
• and
• randomly varying the length of units of the program information for the second block chain in accordance with a length determination circuit.

A method for processing program information, comprising the steps of:

• storing at least one block of the program information in a secure circuit that includes a central processing unit (CPU) and at least one block buffer;
• storing the program information external to said secure circuit in an external storage device;
• communicating a group of blocks of said program information from said external storage device to said at least one block buffer in a first block chain via a first communication path;
• and
• communicating the program information from the at least one block buffer to the CPU for processing therein via a second communication path;
• wherein:
• said program information comprises a plurality of strings of instructions which are to be executed by said CPU in a first sequence;
• in said first block chain, the strings of instructions are provided in a second sequence that differs from the first sequence;
• and
• said secure circuit includes a re-ordering means that is associated with the at least one block buffer for re-ordering the strings of instructions to the first sequence.