US 6,061,418 AGranted

Variable clock divider with selectable duty cycle

AssigneeXilinx, Inc.

InventorJoseph H. Hassoun

Life of this patent

Estimating the term…

Loading patent…

Abstract

A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a rising-edge control signal and a falling-edge control signal. An output generator drives rising edges on the output clock signal in response to active edges on the rising-edge control signal. Conversely, the output generator drives falling edges on the output clock signal in response to active edges on the falling-edge control signal. The frequency of the rising-edge control signal and the frequency of the falling-edge control signal are variable. Common settings for the frequency of the rising-edge control signal and the falling-edge control signal include the frequency of the input clock signal divided by an integer.

Claims18

Dependent claims

A variable clock divider circuit for generating an output clock signal from an input clock signal, the variable clock divider circuit comprising:

a controller coupled to receive the input clock signal and configured to generate a rising-edge control signal having a plurality of active edges, and a falling-edge control signal having a plurality of active edges, the controller having:
a first flip-flop having an input terminal, an output terminal, a set terminal, and a clock input terminal coupled to receive the input clock signal;
a second flip-flop having an input terminal coupled to the output terminal of the first flip-flop, a reset terminal, an output terminal and a clock input terminal coupled to receive the input clock signal;
a third flip-flop having an input terminal coupled to the output terminal of the second flip-flop, a reset terminal, an output terminal, and a clock input terminal coupled to receive the input clock signal;
a first multiplexer having an output terminal coupled to the input terminal of the first flip-flop, a first input terminal coupled to the input terminal of the second flip-flop, and a second input terminal coupled to the input terminal of the third flip-flop;
and
a power-on/reset line coupled to the set terminal of the first flip-flop, the reset terminal of the second flip-flop, and the reset terminal of the third flip-flop;
and
an output generator coupled to the controller and providing the output clock signal, the output generator driving a rising edge on the output clock signal in response to active edges of the rising-edge control signal and driving a falling edge on the output clock signal in response to active edges of the falling-edge control signal.

6 more elements

A variable clock divider circuit for generating an output clock signal from an input clock signal, the variable clock divider circuit comprising:

a controller coupled to receive the input clock signal and configured to generate a rising-edge control signal having an active state and an inactive state, and a falling-edge control signal having an active state and an inactive state;
a precision duty cycle control circuit coupled to receive the input clock signal and configured to generate a precision rising-edge signal having a plurality of active edges, and a precision falling-edge signal having a plurality of active edges;
and
an output generator coupled to the controller and the precision duty cycle control circuit, wherein:
the output generator drives a rising edge on the output clock signal in response to active edges of the precision rising-edge signal when the rising-edge control signal is in the active state of the rising-edge control signal;
and
the output generator drives a falling edge on the output clock signal in response to an active edge of the precision falling-edge signal when the falling-edge control signal is in the active state of the falling-edge control signal.

4 more elements

Dependencies are inferred from the claim text.