US 6,061,296 AGranted

Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices

AssigneeVanguard International Semiconductor Corporation

InventorsLuigi Ternullo, Jr., Christopher Ematrudo, Michael C. Stephens, Jr.

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Abstract

A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

Claims31

Dependent claims

A method for accessing data in a memory array, the method comprising:

sensing a bit in the memory array;
generating a first clock signal, the first clock signal having a first pulse;
generating a second clock signal, the second clock signal having a second pulse;
generating a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse;
and
propagating a signal representing a logic level of the bit to an output line through a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage being coupled to a first interconnect and a second interconnect, the second stage being coupled to the second interconnect and the output line, wherein:
the first interconnect is configured to receive a first data signal that is dependent on the logic level of the bit;
the second pulse causes the first stage to generate on the second interconnect a second data signal as a function of the first data signal;
and
the third pulse causes the second stage to generate onto the output line an output signal that is dependent on the second data signal, and
wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.

8 more elements

A circuit for accessing data in a memory array, the circuit comprising:

a timing circuit configured to provide:
a first clock signal, the first clock signal having a first pulse;
a second clock signal, the second clock signal having a second pulse;
and
a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse;
a first sense amplifier coupled to the memory array, wherein the first sense amplifier is configured to sense a bit in the memory array;
a first interconnect coupled to the first sense amplifier, wherein the first interconnect is configured to receive a first data signal that is dependent from the bit;
a second sense amplifier coupled to the first interconnect, wherein, in response to the second pulse, the second sense amplifier is configured to generate a second data signal as a function of the first data signal;
a second interconnect coupled to receive the second data signal;
and
a third sense amplifier coupled to the second interconnect, wherein, in response to the third pulse, the third sense amplifier is configured to output onto an output line an output data signal as a function of the second data signal;
wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/135,252Filed 17 Aug 1998
Granted: 9 May 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 7/1039
Read-write modes for single port memories, i.e. having either a random port or a serial port: using pipelining techniques, i.e. using latches…
G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…