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US 6,061,278 AGranted
Semiconductor memory, data read method for semiconductor memory and data storage apparatus
AssigneeFujitsu Limited
InventorsYoshiharu Kato, Nobuyoshi Nakaya
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises a plurality of memory cells for storing cell data. Word lines are connected to the memory cells. A first bit line includes a primary bit line connected to each memory cell and a secondary bit line. A first switching circuit is connected between the primary and secondary bit lines. A sense amplifier is connected to the secondary bit line. A second bit line is connected to the sense amplifier. A second switching circuit is connected between the second bit line and one of the primary and secondary bit lines.
Claims52
A semiconductor memory device comprising:
- a plurality of memory cells for storing data;
- word lines connected to said memory cells;
- a first bit line including a primary bit line connected to said memory cells and a secondary bit line;
- a first switching circuit connected between the primary and secondary bit lines;
- a sense amplifier connected to the secondary bit line;
- a second bit line connected to the sense amplifier;
- and
- a second switching circuit connected between the second bit line and one of the primary and secondary bit lines.
5 more elements
A semiconductor memory device comprising:
- a plurality of primary bit lines;
- a first switching circuit connected to each primary bit line;
- a secondary bit line connected to the first switching circuit, the secondary bit line and one of the primary bit lines forming a first bit line;
- a sense amplifier connected to the secondary bit line for receiving a first predetermined potential from a first power supply and a second power supply;
- a second bit line connected to the sense amplifier;
- a second switching circuit connected between the second bit line and the secondary bit line;
- and
- a clamping circuit, connected to each primary bit line, for clamping a potential of the associated primary bit line between the first power supply potential and the second power supply potential.
5 more elements
A semiconductor memory device for reading data stored in a plurality of memory cells, the device comprising:
- word lines connected to said memory cells;
- a first bit line and a second bit line, each of the first and second bit lines connected to one of the word lines via one of the memory cells, and each of the first and second bit lines including a primary bit line and a secondary bit line;
- a pair of first switching circuits, one of the first switching circuits connected between the primary and secondary bit lines of the first bit line, the other first switching circuit connected between the primary and secondary bit lines of the second bit line;
- a sense amplifier connected between the secondary bit lines;
- and
- a second switching circuit connected between the secondary bit lines.
3 more elements
A semiconductor memory device comprising:
- a plurality of memory cells for storing data;
- a plurality of word lines respectively connected to the plurality of memory cells;
- a first bit line including a plurality of primary bit lines and a secondary bit line, each of the primary bit lines connected to an associated one of the memory cells;
- a plurality of first switching circuits, each connected between one of the primary bit lines and the secondary bit line;
- a sense amplifier connected to the secondary bit line;
- a second bit line connected to the sense amplifier;
- and
- a second switching circuit connected between the second bit line and the secondary bit line.
5 more elements
A data storage apparatus comprising:
- a plurality of memory cells;
- a reading device for reading data stored in the plurality of memory cells;
- and
- a reset circuit for resetting the data in the memory cells by writing the same data into at least two memory cells, wherein the reading memory device comprises:
- word lines connected to said memory cells;
- a first bit line, including a primary bit line and a secondary bit line, connected to each memory cell;
- a first switching circuit connected between the primary and secondary bit lines;
- a sense amplifier connected to the secondary bit line;
- a second bit line connected to the sense amplifier;
- and
- a second switching circuit connected between the second bit line and one of the primary and secondary bit lines.
8 more elements
A method for reading data in a semiconductor memory device, the method comprising the steps of:
- providing a semiconductor memory device comprising:
- a plurality of memory cells for storing data;
- word lines connected to said memory cells;
- a first bit line including a primary bit line connected to said memory cells and a secondary bit lines;
- a first switching circuit connected between the primary and secondary bit lines;
- a sense amplifier connected to the secondary bit line;
- a second bit line connected to the sense amplifier;
- and
- a second switching circuit connected between the second bit line and one of the primary and secondary bit lines;
- setting an output terminal of the sense amplifier to a high impedance state by deactivating the sense amplifier;
- precharging the first and second bit lines by connecting the first and second bit lines to each other to distribute charges stored therein, wherein the first bit line includes the primary and secondary bit lines and has a capacitance greater than that of the second bit line;
- reading data on the secondary bit line;
- disconnecting the primary bit line from the secondary bit line;
- and
- generating read data by amplifying the potential difference between the secondary bit line and the second bit line with the sense amplifier.
12 more elements
A method for reading data stored in a semiconductor memory device, the method comprising the steps of:
- providing the semiconductor memory device comprising:
- a plurality of memory cells for storing data;
- a plurality of word lines respectively connected to the memory cells;
- a first bit line including a plurality of primary bit lines and a secondary bit line, each of the primary bit lines connected to one of the associated memory cells;
- a plurality of first switching circuits, each connected between one of the primary bit lines and the secondary bit line;
- a sense amplifier connected to the secondary bit line;
- a second bit line connected to the sense amplifier;
- and
- a second switching circuit connected between the second bit line and the secondary bit line;
- setting an output terminal of the sense amplifier to a high impedance state by deactivating the sense amplifier;
- precharging the first and second bit lines by connecting the first and second bit lines together to distribute charges stored therein, wherein the primary bit lines and the secondary bit line, having a capacitance greater than that of the second bit line;
- selecting a world line connected to the memory cell associated with the primary bit line such that the primary bit lines are connected to the secondary bit line in order;
- reading data on the secondary bit line via the primary bit line from the associated memory cell;
- disconnecting the primary bit line from the secondary bit line;
- and
- generating read data by amplifying the potential difference between the secondary bit line and the second bit line with the sense amplifier.
13 more elements
A method for reading data in a semiconductor memory device, the method comprising the steps of:
- providing the semiconductor memory device comprising:
- a plurality of primary bit lines;
- a first switching circuit connected to each of the primary bit lines;
- a secondary bit line connected to the first switching circuit, the secondary bit line and the primary bit lone forming a first bit line;
- a sense amplifier connected to the secondary bit line for receiving a first predetermined potential from a first power supply and a second predetermined potential from a second power supply;
- a second bit line connected to the sense amplifier;
- a second switching circuit connected between the second bit line and the secondary bit line;
- and
- a clamping circuit connected to each of the primary bit lines for clamping the potential of the associated primary bit line between the first power supply potential and the second power supply potential;
- setting an output terminal of the sense amplifier to a high impedance by deactivating the sense amplifier;
- precharging the first and second bit lines by connecting the bit lines together to distribute charges stored therein, wherein the plurality of primary bit lines and the secondary bit line have a capacitance greater than that of the second bit line;
- selecting a world line connected to the clamp circuit associated with the primary bit line such that the primary bit lines are connected to the secondary bit line in order;
- reading data on the secondary bit line via the primary bit line from the associated clamp circuit;
- disconnecting the primary bit line from the secondary bit line;
- and
- generating read data by amplifying the potential difference between the secondary bit line and the second bit line with the sense amplifier.
13 more elements
Dependencies are inferred from the claim text.