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US 6,060,930 AGranted
Delay circuit
AssigneeLG Semicon Co., Ltd.
InventorHong-Sok Choi
Life of this patent
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Abstract
A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.
Claims20
A circuit, comprising:
- a plurality of delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor for coupling to a ground potential and connected to an output terminal of the inverter, wherein the variable capacitor includes a transistor having a substrate for coupling to an adjustable voltage to modulate a capacitive value of the variable capacitor.
A delay circuit, comprising:
- a plurality of inverters coupled in series;
- and
- a variable capacitor including a variable transistor having
- a first electrode coupled to an output of one of the inverters,
- a source and drain commonly connected to form a second electrode for coupling to a ground potential, and
- a substrate for coupling to a variable voltage to modulate a capacitive value of the variable capacitor.
3 more elements
A delay circuit, comprising:
- series means for coupling a plurality of inverters in series, each inverter for coupling to a first potential;
- and
- means for preventing a delay time that varies according to the first potential, the means for preventing including,
- a transistor having a gate electrode, a source electrode, a drain electrode and a substrate,
- means for coupling the gate electrode to an output of one of the inverters,
- means for commonly connecting the source electrode and the drain electrode for coupling to a second potential, and
- means for modulating a capacitive value of the means for preventing by coupling a variable voltage to the substrate.
4 more elements
Dependencies are inferred from the claim text.