Universal signal processor and method of processing

Abstract

A method for decoding and reconstructing a scrambled video signal is provided in which a scrambled video signal is received and the location of at least one predetermined element of the scrambled video signal is determined. Next, a horizontal sync is generated at the proper location of an output signal in response to the location of the at least one predetermined element of the scrambled video signal. Finally, the remainder of the scrambled video signal is output as an unscrambled video signal. A method of encoding a video signal is also provided, which comprises the steps of receiving an unscrambled video signal and producing a scrambled video signal by altering at least one predetermined element of the unscrambled video signal without providing encoding data to aid in the decoding of the scrambled video signal. An apparatus for decoding and reconstructing a scrambled video signal is also provided, which comprises a tuner for receiving and tuning a scrambled video signal and a transition tester coupled with the tuner for testing the scrambled video signal to determine the location of at least one predetermined element of the video signal. A video processor receiving an indication substantially corresponding to the determination of the at least one predetermined element from the transition tester is also provided. The video processor generates and outputs a horizontal sync in response to the indication from the transition tester. A selector coupled with the video processor outputs the remainder of the scrambled video signal as an unscrambled video signal.

Dependencies are inferred from the claim text.