Signal processors
AssigneesSony Corporation, Sony United Kingdom Limited
InventorsPeter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
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AssigneesSony Corporation, Sony United Kingdom Limited
InventorsPeter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
Estimating the term…
An nth order Delta Sigma Modulator (DSM) where n.gtoreq.1, comprising an input (4) for receiving a 1-bit input signal having a signal component and a noise component, a quantifier (Q) for re-quantizing a p-bit signal (where p>1) to 1-bit form, the re-quantised 1-bit signal being the output signal of the DSM, a first combiner (a, A, 61, 71) for forming the integral (71) of an additive (61) combination of the product of the input 1-bit signal and a coefficient (a) and of the product of the output signal and a coefficient (A), n-1 intermediate combiners each for forming the integral of an additive combination of the product of the input 1-bit signal and a coefficient, of the product of the output signal and a coefficient and of the integral of the additive combination of the preceding combiner and a final combiner (d, 64) for forming an additive combination (64) of the input signal and a coefficient (d) and of the integral of the combiner of the preceding combination to form the said p-bit signal re-quantised by the quantifier (Q), wherein the transfer function applied by the DSM to the input 1-bit signal is ##EQU1## the transfer function applied to the quantized noise introduced by the quantizer is ##EQU2## wherein at least one of a.sub.1 to a.sub.n equals +1, and each of b.sub.1 to b.sub.n is not equal to +1.
An n th order Delta Sigma Modulator (DSM) where n.gtoreq., comprising an input for receiving a 1-bit input signal having a signal component and a noise component,
An n th order DSM where n.gtoreq.2, comprising an input for receiving a 1-bit input signal having a signal component and a noise component,
An n th order Delta Sigma Modulator (DSM) where .gtoreq.2, comprising an input for receiving a 1-bit input signal having a signal component and a noise component,
A plurality of Delta Sigma Modulators arranged in series, each of said Delta Sigma Modulators comprising an n th order Delta Sigma Modulator (DSM) where n.gtoreq.1, comprising an input for receiving a 1-bit input signal having a signal component and a noise component;
A plurality of Delta Sigma Modulators (DSM) arranged in series, each of said Delta Sigma Modulators comprising an n th order DSM where n.gtoreq.2, comprising an input for receiving a 1-bit input signal having a signal component and a noise component;
A plurality of Delta Sigma Modulators arranged in series, each of said Delta Sigma Modulators comprising an n th order Delta Sigma Modulator (DSM) where n.gtoreq.2, comprising an input for receiving a 1-bit input signal having a signal component and a noise component, a quantizer for re-quantizing a p-bit signal (where p>1) to 1-bit form, the re-quantised 1-bit signal being the output signal of the DSM;
Dependencies are inferred from the claim text.