Electropolishing copper film to enhance CMP throughput
AssigneeAdvanced Micro Devices, Inc.
InventorRobin W. Cheung
Life of this patent
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Abstract
In-laid metal, e.g., copper or copper alloy, contacts and conductive routing patterns are formed in recesses in the surface of a substrate by a damascene-type process, comprising depositing a layer of an electrically conductive material filling the recesses and covering the substrate surface, reducing the thickness of the layer by a process providing a faster rate of layer removal than that obtained by chemical-mechanical polishing (CMP), and subjecting the remaining layer thickness to CMP processing to (a) substantially remove the remaining layer thickness and (b) render the exposed upper surface of the material filling the recesses substantially coplanar with the substrate surface, whereby increased manufacturing throughput, greater planarity, and reduced defects are obtained.
Claims17
A method of forming a layer of an electrically conductive material filling at least one recessed area formed in a substrate surface and having an exposed upper surface substantially coplanar with said substrate surface, the method comprising the sequential steps of:
- (a) providing a substrate having a surface comprising at least one recessed area and at least one non-recessed area;
- (b) depositing a layer of an electrically conductive material over said surface, said layer overfilling the at least one recessed area and covering the at least one non-recessed area to a first thickness;
- (c) reducing the first thickness of said layer to a second thickness by a wet process having a faster rate of layer removal than chemical-mechanical polishing (CMP);
- (d) chemical-mechanical polishing the remaining second thickness of said layer to substantially remove the portions thereof covering the at least one non-recessed area of the substrate surface and render the exposed upper surface of the portion filling the at least one recess substantially coplanar with the substrate surface, whereby increased manufacturing throughput, increased uniformity, and reduced defects are obtained as compared to removing the entire layer thickness by CMP.
A method of manufacturing a semiconductor device, the method comprising the sequential steps of:
- providing a substrate comprising a semiconductor having thereon a dielectric layer with a surface comprising at least one recessed area and at least one non-recessed area;
- electrodepositing a layer of copper or copper alloy over said surface to a first thickness, said layer overfilling the at least one recessed area and covering the at least one non-recessed area;
- electrolytically reducing the first thickness of said layer to a second thickness;
- and
- chemical-mechanical polishing (CMP) the remaining second thickness of said layer to (a) substantially remove the portions thereof covering the at least one non-recessed area of the substrate surface and (b) render the exposed upper surface of the portion filling the at least one recess substantially coplanar with the substrate surface.
Dependencies are inferred from the claim text.