Semiconductor integrated circuit device and method of testing the same
AssigneeKabushiki Kaisha Toshiba
InventorTomomi Momohara
Life of this patent
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Abstract
Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.
Claims11
A method of testing a semiconductor integrated circuit device comprising a semiconductor substrate, said substrate constituting a separating region, a plurality of integrated circuit formation regions formed in the separating region, said integrated circuit formation regions being independent of each other, and integrated circuits formed in the integrated circuit formation regions, respectively, said integrated circuits having dedicated power supplies,
- said method comprising the steps of:
- supplying power to one of the integrated circuits to be tested;
- testing the integrated circuit to be tested;
- stopping supply of the power to the tested integrated circuit after the test is finished, and supplying power to another integrated circuit to be tested;
- and
- testing the another integrated circuit.
A semiconductor integrated circuit comprising device:
- a semiconductor substrate of a first conductivity type;
- at least one first well of a second conductivity type, formed in the semiconductor substrate;
- an integrated circuit formed in the first well;
- a power supply system including a high-potential power line and a low-potential power line for supplying an operational voltage to the integrated circuit;
- a bias system for supplying a bias potential to the semiconductor substrate, the bias system including a bias line separated from the high-potential power line and the low-potential power line;
- a first pad connected to the bias line;
- a second pad connected to the high-potential power line;
- and
- a third pad connected to the low-potential power line.
A tester for a semiconductor integrated circuit, the tester comprising:
- a supply voltage generator, associated with a plurality of semiconductor integrated circuit device chips to be tested at a time, for generating a supply voltage for operating integrated circuits on each semiconductor integrated circuit device chip;
- a detector for detecting a variation in supply voltage for each semiconductor integrated circuit device chip, while the semiconductor integrated circuit device chips are being tested;
- a judgement circuit device for determining whether the variation in supply voltage detected for each chip falls within a predetermined range of allowance;
- and
- a switch control circuit and driver circuit for shutting off, when it has been determined that the variation in supply voltage detected for each chip falls outside the predetermined range of allowance, the supply of the supply voltage to the chip with the variation in supply voltage outside the predetermined range of allowance.
Dependencies are inferred from the claim text.