Circuits, system, and methods for processing multiple data streams

An audio information processing subsystem fabricated on a single-integrated circuit chip comprising:

• a stream processor for simultaneously processing multiple streams of audio data;
• a program memory coupled to said stream processor by a first bus for storing instructions for controlling said processing subsystem;
• data memory coupled to said stream processor by a second bus;
• and
• direct memory access circuitry for controlling direct memory accesses to a selected one of said program and data memories, said direct memory access circuitry defining a plurality of buffers in said data memory, each buffer associated with one of said data streams.

A multiply-accumulate unit comprising:

• a multiply-accumulate path for processing a channel of audio data comprising:
• first input circuitry for selectively receiving an M-bit wide coefficient word;
• second input circuitry for selectively receiving an N-bit wide data word;
• an M-bit by N-bit two's complement multiplier array receiving data and coefficients from said input circuitry and outputting a sum vector and a carry vector in response;
• a P-bit wide carry-save adder for adding said sum and carry vectors and an accumulator output;
• a P-bit wide adder for adding first and second outputs of said carry-save adder;
• at lest one P-bit wide accumulator for storing data output from said adder;
• and
• circuitry for selectively feeding-back data from said at least one accumulator to said carry-save adder.

A stream processing system comprising:

• a PCI bus;
• a host processing subsystem coupled to said PCI bus including:
• a central processing unit;
• a host memory;
• and
• circuitry for interfacing said central processing unit and said host memory with said PCI bus;
• and
• a stream processing subsystem coupled to said PCI bus including:
• a stream processor for processing a plurality of streams of data simultaneously received, said stream processor including a direct memory access engine operable to exchange information with said host system using direct memory accesses, said direct memory access circuitry controlling a plurality of buffers in memory, each said buffer associated with a corresponding one of said streams of data;
• and
• circuitry for interfacing said stream processor with a source of multiple streams of data.