Control system and method for semiconductor integrated circuit test process

A method of specifying quality assurance testing of integrated circuit devices, said method comprising the steps of:

• loading a tester with a test program, and identifying IC devices to be tested by the tester by lot;
• testing each of the IC devices of a said lot under a plurality of test sequences, and sorting the IC devices of the lot into bin categories according to results of the test sequences, the test sequences each defining a pass or fail standard for the IC devices;
• monitoring progress of the testing of the lot of IC devices, while storing test result data indicative of the results of the test sequences;
• establishing limits for each of the bin categories;
• when the testing and sorting is completed, making a lot decision governing a subsequent test flow path of a tested lot by using the stored test result data and the bin category limits, said making of the lot decision including determining whether the lot meets a yield requirement of the test sequences;
• storing the test result data in different memory locations in a computer in accordance with the lot decision, and displaying the lot decision;
• and
• executing quality assurance test decisions when the lot meets the yield requirement, said quality assurance test decisions including:
• if the tested lot has a quantity of IC devices exceeding the bin category limits, which quantity is equal to or greater than a predetermined number, then performing both a sampling test and a production reliability test on IC devices in the lot which have passed the test sequences,
• if the tested lot has a quantity of IC devices exceeding the bin category limits, which quantity is less than the predetermined number, then performing only the sampling test only on the IC devices in the lot which have passed the test sequences, and
• if the tested lot has no IC devices exceeding the bin category limits, then omitting the sampling test and the production reliability test.