Systems and method having data encoded with edge placement equalization

A method for encoding an input signal to provide an output signal, the input signal comprising sequential input bits, the output signal comprising sequential cells, each cell comprising a respective reference time, wherein for each cell, a bit in a first state is to be represented by a data transition and a bit in a second state is to be represented by the absence of a data transition, the method comprising:

• providing a timing signal having a period between consecutive active edges;
• providing, in response to a first active edge, a first equalization transition in a first cell in further response to detecting the occurrence of two consecutive bits each in the second state;
• and
• providing, in response to a second active edge, a first data transition at an offset from the respective reference time of a second cell in further response to detecting the occurrence of a bit in the second state, wherein the offset comprises a period of the timing signal.

A circuit that receives a data signal, comprising a series of bits, and provides an output signal responsive to the data signal and according to an asymmetric write equalization scheme, the circuit comprising:

• a state machine for providing the output signal, the output signal comprising in sequence:
• a. a first write equalization transition;
• b. first data transition a predetermined integer number of periods of a clock signal after the first write equalization transition;
• c. a second data transition;
• and
• d. a second write equalization transition the predetermined integer number of periods of the clock signal after the second data transition.