Asynchronous register
AssigneeTheseus Logic, Inc.
InventorKarl Fant
Life of this patent
Estimating the term…
Abstract
A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine).
Claims17
An asynchronous register comprising:
- an input receiving a plurality of asynchronous data signals;
- an input receiving a control signal;
- a plurality of asynchronous storage elements, each asynchronous storage element generating an output signal in response to at least one of the plurality of asynchronous data signals and the control signal;
- wherein each asynchronous storage element is characterized by asserting a meaningful output when the asynchronous data signal and the control signal are meaningful, and holding the meaningful output until both the asynchronous data signal and the control signal are non-meaningful;
- and
- wherein each asynchronous storage element is further characterized by switching its output to a non-meaningful signal when the asynchronous data signal and the control signal are non-meaningful, and holding the non-meaningful output until both the asynchronous data signal and the control signal are meaningful.
An asynchronous circuit for storing logic values that are expressed on a plural set of transmission lines, where each transmission line may assume an asserted state having a logical meaning and a non-meaningful state that lacks a logical meaning, and where transmission lines are organized into at least one mutually exclusive assertion group, said mutually exclusive assertion group characterized by having at most one transmission line at a time in the asserted state, said asynchronous circuit comprising:
- a first plural set of input transmission lines grouped into at least one mutually exclusive assertion group;
- a first plural set of storage cells connected to the input transmission lines, said storage cells alternately storing logic values expressed on the input transmission lines and non-meaningful states;
- a first plural set of output transmission lines grouped into at least one mutually exclusive assertion group and expressing at least one logic value stored in the storage cells;
- and
- a first feedback circuit generating a first feedback signal, said first feedback signal transitioning to a first state when all output transmission lines are in the non-meaningful state and transitioning to a second state when a predetermined number output transmission lines are in the asserted state, wherein said predetermined number is greater than or equal to the number of mutually exclusive assertion groups in the output transmission lines and less than the number of output transmission lines.
A method of storing a logic value in storage cells, where each storage cell is capable of assuming an asserted storage state having a logical meaning and a non-meaningful storage state that lacks logical meaning, the method comprising steps of:
- establishing a first plural set of cells in the non-meaningful storage state;
- expressing a first logic value on a first plural set of transmission lines, where each of the first plural set of transmission lines may assume an asserted state having a logical meaning and a non-meaningful state that lacks logical meaning, and where the first plural set of transmission lines are organized into a mutually exclusive assertion group characterized by having at most one transmission line at a time in the asserted state at a time;
- communicating the first logic value expressed on the first plural set of transmission lines to the first plural set of storage cells at a time when all of the first plural set of storage cells are in the non-meaningful storage state;
- and
- storing the first logic value by switching at least one storage cell of the first plural set of storage cells from the non-meaningful storage state to the asserted storage state.
Dependencies are inferred from the claim text.