Shift register using M.I.S. transistors of like polarity
AssigneeThomson-LCD
InventorFran.cedilla.ois Maurice
Life of this patent
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Abstract
The subject of the present invention is a shift register for an LCD, the stages of which use the Boostrap [sic] effect and can contain just three M.I.S. transistors, as well as enhancements to this circuit with four or seven MIS transistors. The advantages are the low number of components used, the increase in the lifetime of the shift register and the possibility of working with control signals having an amplitude of 5 or 10 v below that of the output signals.
Claims38
Shift register containing a plurality of cascaded stages, a given stage being responsive to two clock signals, said given stage having an output and being coupled to an output of a preceding stage and to an output of a next stage, said given stage comprising:
- a first semiconductor output device switching the output of said given stage between high and low values of a first clock signal, the first semiconductor device being controlled by the potential of a first node connected:
- to the output of the preceding stage via a second semiconductor device controlled by the output of the preceding stage,
- to a negative potential via a third semiconductor device controlled by the output of the next stage,
- to a second clock signal via a first capacitance,
- and to the output of the given stage via a second capacitance.
Shift register containing a plurality of cascaded stages, a given stage being responsive to two clock signals, said given stage having an output and being coupled to an output of a preceding stage, and to an output of a next stage, the given stage comprising:
- a first semiconductor output device switching the output of said given stage between high and low values of a first clock signal, the first semiconductor device being controlled by the potential of a first node connected:
- to the output of the preceding stage via a second semiconductor device controlled by this same preceding stage output,
- to a second clock signal via a first capacitance,
- to the output of said given stage via a second capacitance, the given stage output being connected to earth via a third semiconductor device controlled by a second node,
- and to earth across a fourth semiconductor device controlled by the second node, the second node being further connected:
- to the output of the preceding stage via a fourth capacitance,
- to earth via a fifth semiconductor device controlled by the output of the preceding stage,
- to the output of the next stage via sixth and seventh clamping transistors mounted in parallel and controlled, one by the second node and the other by the output of the next stage,
- and to a terminal of the third semiconductor device connected to earth, by a fifth capacitance.
Shift register containing a plurality of cascaded stages, a given stage being responsive to two clock signals, said given stage having an output and being coupled to an output of a preceding stage and to an output of one of a next stage and of a stage following the next stage, the given stage comprising:
- a first semiconductor output device switching a selection line connected to the output of the given stage between high and low values of a first clock signal, the first semiconductor device being controlled by the potential of a first node connected:
- to the output of the preceding stage via a second semiconductor device controlled by the preceding stage output,
- to a second clock signal via a first capacitance,
- to the output of the given stage via a second capacitance, the given stage output being connected to earth via a fourth semiconductor device controlled by a second node, and
- to a negative potential via a third semiconductor device controlled by the second node which is further connected to one of the output of the next stage and of the stage following the next stage.
Shift register containing a plurality of cascaded stages, a given stage being responsive to two clock signals, said given stage having an output and being coupled to an output of a preceding stage and to an output of a next stage, said given stage comprising:
- a first semiconductor output device switching the given stage output between high and low values of a first clock signal, the first semiconductor device being controlled by the potential of a first node connected:
- to the output of the preceding stage via a second semiconductor device controlled by the preceding stage output,
- to a signal via a third semiconductor device controlled by the output of the next stage,
- to a second clock signal via a first capacitance,
- and to the output of the given stage via a second capacitance, the given stage output being connected to earth via a fourth semiconductor device controlled by a zero-reset signal.
Shift register containing a plurality of cascaded stages, a given stage being responsive to two clock signals, said given stage having an output and being coupled to an output of a preceding stage and to an output of a next stage, said given stage comprising:
- a first semiconductor output device switching the output of said given stage between high and low values of a first clock signal, the first semiconductor device being controlled by the potential of a first node connected:
- to the output of the preceding stage via a second semiconductor device controlled by this same preceding stage output,
- to a constant negative potential via a third semiconductor device controlled by a clock signal chosen from three clock signals,
- to a second clock signal via a first capacitance,
- and to the output of the given stage via a second capacitance, the given stage output being connected to earth via a fourth semiconductor device controlled by a zero-reset signal.
Dependencies are inferred from the claim text.