Bit-wise conditional write method and system for an MRAM

In an integrated circuit (IC) magnetic random access memory (MRAM) system having at least one word consisting of n data bits, and one complement bit, each of said bits comprising an MRAM cell which is writeable in a selected one of a first and a second logic state in response to a coincidence of a word.sub.-- write current and a bit.sub.-- write current, a write method comprising the steps of:

• receiving n input bits, each having one of said first and second logic states;
• reading said cells to determine the current logic states of said data bits and said complement bit;
• comparing the logic state of each of said n input bits to the current logic state of a respective one of said n data bits;
• if the logic states of a majority of said n input bits are different from the logic states of the corresponding ones of said n data bits, providing a complement signal in a selected one of said first and second logic states;
• in response to said complement signal being provided in said selected state, conditionally complementing each of said input bits;
• providing said word.sub.-- write current;
• for each of said n data bits, providing said bit.sub.-- write current if the logic state of the respective one of said conditionally complemented input bits is different from the current logic state of said data bit;
• and
• for said complement bit, providing said bit.sub.-- write current if the logic state of said complement signal is different from the current logic state of said complement bit.

In an integrated circuit (IC) magnetic random access memory (MRAM) system having at least one word consisting of at least one data bit, said data bit comprising an MRAM cell which is writeable in a selected one of a first and a second logic state in response to a coincidence of a word.sub.-- write current and a bit.sub.-- write current, a write control circuit comprising:

• a word.sub.-- write driver circuit which, when enabled, provides said word.sub.-- write current;
• a bit.sub.-- write driver circuit which, when enabled, provides said bit.sub.-- write current;
• and
• a comparison circuit to compare an input bit having one of said first and second logic states to the current logic state of said data bit, and to simultaneously enable said word.sub.-- write driver circuit and said bit.sub.-- write driver circuit if the logic state of said input bit is different from the current logic state of said data bit.

In an integrated circuit (IC) magnetic random access memory (MRAM) system having at least one word consisting of n data bits, and one complement bit, each of said bits comprising an MRAM cell which is writeable in a selected one of a first and a second logic state in response to a coincidence of a word.sub.-- write current and a bit.sub.-- write current, a write control circuit comprising:

• a word.sub.-- write driver circuit which, when enabled, provides said word.sub.-- write current;
• n data.sub.-- bit.sub.-- write driver circuits, each of which, when enabled, provides said bit.sub.-- write current to a respective one of said n data bits;
• a complement.sub.-- bit.sub.-- write driver circuit which, when enabled, provides said bit.sub.-- write current to said complement bit;
• a complement circuit which, in response to a complement signal in a predetermined one of said first and second logic states, conditionally complements each of n input bits, each having one of said first and second logic states;
• a first comparison circuit to compare the current logic state of each of said data bits to the logic state of a respective one of said n input bits, and, if the current logic states of a majority of said n data bits are different from the logic states of the corresponding ones of said n input bits, to provide said complement signal in said predetermined logic state;
• and
• a second comparison circuit, connected to the complement circuit and each of said driver circuits, to compare the logic state of each of said conditionally complemented n input bits to the current logic state of a respective one of said n data bits, and to simultaneously enable:
• said word.sub.-- write driver circuit;
• said data.sub.-- bit.sub.-- write driver circuit of each of said respective n data bits if the current logic state thereof is the different from the logic state of the respective one of said conditionally complemented input bits;
• and
• said complement.sub.-- bit.sub.-- write driver circuit if the current logic state of said complement bit is different from the logic state of said complement signal.

In an integrated circuit (IC) random access memory system having at least one word consisting of n data bits, and one complement bit, each of said bits being writeable in a selected one of a first and a second logic state, a word-wise conditional write method comprising the steps of:

• receiving n input bits, each having one of said first and second logic states;
• reading said cells to determine the current logic states of said data bits and said complement bit;
• comparing the logic state of each of said n input bits to the current logic state of a respective one of said n data bits;
• if the logic states of a majority of said n input bits are different from the logic states of the corresponding ones of said n data bits, providing a complement signal in a selected one of said first and second logic states;
• in response to said complement signal being provided in said selected state, conditionally complementing each of said input bits;
• for each of said n data bits, if the logic state of the respective one of said conditionally complemented input bits is different from the current logic state of said data bit, writing said data bit to the logic state of said respective one of said complemented input bits;
• and
• for said complement bit, if the logic state of said complement signal is different from the current logic state of said complement bit, writing said complement bit to the logic state of said complement signal.