CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics

An operational amplifier integrated circuit, comprising:

• a differential input stage;
• a cascode current mirror electrically coupled to said differential input stage and between a differential output and a first reference potential;
• a cascode current source electrically coupled to said differential input stage and between the differential output and a second reference potential;
• means, electrically coupled to said differential input stage, said cascode current mirror and said cascode current source, for sequentially enabling said cascode current mirror and then said differential input stage in response to a first control signal transition;
• and
• a common mode feedback circuit;
• and
• wherein said sequentially enabling means comprises means for generating first through sixth bias signals on first through sixth bias signal lines, respectively.

An operational amplifier integrated circuit, comprising:

• a differential input stage;
• a cascode current mirror electrically coupled to said differential input stage and between a differential output and a first reference potential;
• a cascode current source electrically coupled to said differential input stage and between the differential output and a second reference potential;
• and
• a bias signal generator, responsive to a clock signal and electrically coupled to said differential input stage, said cascode current mirror and said cascode current source, to sequentially enable said cascode current mirror and then said differential input stage in response to a first edge of the clock signal and disable said cascode current mirror and said cascode current source in response to a second edge of the clock signal.