Constant impedance, low noise CMOS buffer

A low noise CMOS circuit to provide a constant impedance load and linear ramped current waveform at the circuit output in response to receiving an input signal at a circuit input, the circuit comprising:

• first (Vddp) and second (Vdd) power supply nodes, and first (Vssp) and second (Vss) ground nodes;
• a first pair of driver transistors, with the source of PMOS transistor P5 operatively connected to said first power supply node (Vddp), the drain of said P5 PMOS operatively connected to the output and the drain of NMOS transistor N5, and the source of said N5 NMOS operatively connected to said first ground node (Vssp);
• a second pair of driver transistors operatively connected in parallel to said first transistor pair, with the source of PMOS transistor P6 operatively connected to said first power supply node (Vddp), the drain of said P6 PMOS operatively connected to the output and the drain of NMOS transistor N6, and the source of said N6 NMOS operatively connected to the said ground node (Vssp);
• four pre-driver circuits, which each pre-driver circuit including a transistor pair, with the source of a PMOS transistor (P1, P2, P3, and P4) operatively connected to said second power supply node (Vdd), the drain of said PMOS transistors operatively connected to a pre-driver output and the drain of an NMOS transistor (N1, N2, N3, and N4), and the source of said NMOS transistors operatively connected to said first ground node (Vssp);
• in which a first pre-driver includes said P1 and N1 transistors, with the gates of said P1 and N1 transistors operatively connected to the circuit input to accept the input signal, said first pre-driver output operatively connected to the gate of said driver PMOS P5 to supply the pdrv1 signal;
• in which a second pre-driver includes said P2 and N2 transistors, with the gates of said P2 and N2 transistors operatively connected to the circuit input to accept the input signal, said second pre-driver output operatively connected to the gate of said driver PMOS P6 to supply the pdrv2 signal;
• in which a third pre-driver includes said P3 and N3 transistors, with the gates of said P3 and N3 transistors operatively connected to the circuit input to accept the input signal, said third pre-driver output operatively connected to the gate of said driver NMOS N6 to supply the ndrv2 signal;
• in which a fourth pre-driver includes said P4 and N4 transistors, with the gates of said P4 and N4 transistors operatively connected to the circuit input to accept the input signal, said fourth pre-driver output operatively connected to the gate of said driver NMOS N5 to supply the ndrv1 signal;
• a first NMOS (N7) pullup transistor, with the drain of said N7 NMOS operatively connected to said second power supply node (Vdd), the source operatively connected to said P6 PMOS gate, and the gate operatively connected said N5 NMOS gate;
• a second NMOS (N8) pullup transistor, with the drain of said N8 NMOS operatively connected to said second power supply node (Vdd), the source operatively connected to said P5 PMOS gate, and the gate operatively connected said N5 NMOS gate;
• and
• a first PMOS (P7) pulldown transistor, with the source of said P7 PMOS operatively connected to said N6 NMOS gate, the drain operatively connected to said second ground node (Vss), and the gate operatively connected said N5 NMOS gate, whereby the circuit minimizes the generation of noise at the power nodes, ground nodes, and circuit output.

In a low noise buffer circuit having two pair of parallel pullup pulldown transistors, a method for providing an output having a constant impedance load with a linear ramped current waveform, the method comprising the steps of:

• a) accepting an input signal to be buffered;
• and
• b) performing the following sub-steps in response to the input signal:
• 1) in response to the signal received in Step a), providing a fourth pre-diver signal ndrv1 that is a replica of the compliment of the input signal, with a first ramp duration and a first time delay;
• 2) in response to the signal received in Step a) and the provision of the fourth pre-driver signal in Step a)1), providing a third pre-driver signal ndrv2 that is a replica of the compliment of the input signal, with a second ramp duration, greater than the first, and a second time delay, greater than the first;
• 3) in response to the signal received in Step a), the provision of the fourth pre-driver signal in Step a)1), and the provision of the third pre-driver signal in Step a)2), providing a second pre-driver signal pdrv2 that is replica of the compliment of the input signal, with a third ramp duration, greater than the second ramp duration, and a second time delay;
• 4) in response to the signal received in Step a), the provision of the fourth pre-driver signal in Step a)1), providing a first pre-driver signal pdrv1 that is replica of the compliment of the input signal, with a second ramp duration and a second time delay;
• 5) in response to the fourth pre-driver signal ndrv1, gating a first pulldown driver transistor;
• 6) in response to the third pre-driver signal ndrv2, gating a second putdown driver transistor;
• 7) in response to the second pre-driver signal pdrv2, gating a second pullup driver transistor;
• and
• 8) in response to the first pre-driver signal pdrv1, gating a first pullup driver transistor, whereby a low noise buffer signal is provided.