US 6,049,672 A · Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

Abstract

A microprocessor operates in response to microinstructions stored in a read only memory. A patch table stores a indication of patch microinstructions stored in cache memory. This cache memory caches data and/or macroinstructions for the microprocessor. Each new microaddress is compared with the patch table entries. If there in no match, then a multiplexer selects the microinstruction recalled from that microinstruction address within the microinstruction read only memory. If there is a match, then a corresponding patch microinstruction is recalled from the cache memory. The multiplexer selects this patch microinstruction. The microprocessor operates under the control of the selected microinstruction. This technique enables a fix of faulty microinstructions in the field, by supplying the computer user with the patch microinstructions. Using a portion of the cache memory to store the patch microinstructions eliminates any problem with specifying too large or too small a memory for patch microinstructions.

Claims20

Dependent claims

A processor disposed on a single integrated circuit operable in response to microinstructions, said processor comprising:

a microaddress sequencer generating a next microaddress;
a read only microinstruction memory circuit coupled to said microaddress sequencer, said microinstruction memory circuit storing a plurality of original microinstructions fixed upon manufacture at corresponding microaddresses and operable to output an original microinstruction stored at a microaddress received from said microaddress sequencer in response to a request signal;
a cache memory circuit simultaneously both caching a first type of information different from microinstructions and also storing at least one patch microinstruction, said cache memory circuit coupled to output at least said first type of information and to output a patch microinstruction in response to the request signal;
and
selection circuitry coupled to said microinstruction memory circuit and said cache memory circuit for selecting for control of the processor for a next cycle between the original microinstruction recalled from said microinstruction memory circuit and the patch microinstruction recalled from said cache memory circuit.

2 more elements

A method of operating a microprocessor in response to an identified code, said method comprising the steps of:

storing in a read only microinstruction memory circuit a plurality of original microinstructions fixed upon manufacture at corresponding microaddresses;
issuing a request signal requesting a microinstruction from a next microaddress;
outputting an original microinstruction from a memory location within the microinstruction memory circuit corresponding to the next microaddress in response to the request signal;
simultaneously both caching a first type of information other than microinstructions in a cache memory circuit and also storing at least one patch microinstruction in respective locations in the cache memory circuit;
detecting whether the next microaddress of the request signal corresponds to at least one patch microinstruction;
in response to detecting that the next microaddress of the request signal corresponds to the at least one patch microinstruction, outputting the at least one patch microinstruction from cache memory circuit in response to the request signal;
and
selecting for control of the microprocessor for a next cycle between the at least one original microinstruction recalled from the microinstruction memory circuit and the at least one patch microinstruction recalled from the cache memory circuit.

5 more elements

Dependencies are inferred from the claim text.

Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

Life of this patent

Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

Life of this patent

Abstract

Claims20