# US 6,049,542 A · Scalable multistage interconnection network architecture and method for performing in-service upgrade thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,049,542 A - Document ID: US6049542A - Status: Granted - Kind: A - Application number: 09/002,042 - Filed: 1997-12-31 - Granted: 2000-04-11 - Earliest claimed: 1997-12-31 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Sharat C. Prasad - Web page: https://patentgrep.com/patent/US6049542A ## CPC - H04L 49/203: {ATM switching fabrics with multicast or broadcast capabilities} - H04L 49/106: {using space switching, e.g. crossbar or matrix} - H04L 49/15: Interconnection of switching modules - H04Q 3/68: Grouping or interlacing selector groups or stages - H04Q 2213/13204: Protocols - H04Q 2213/1329: Asynchronous transfer mode, ATM - H04Q 2213/13292: Time division multiplexing, TDM - H04Q 2213/1334: Configuration within the switch - H04Q 2213/13389: LAN, internet - H04Q 2213/13393: Time slot switching, T-stage, time slot interchanging, TSI - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W) ## Abstract There is disclosed a scalable switch fabric architecture comprising: 1) an input switching stage having N inputs and N outputs operable to connect selected ones of the N inputs to selected ones of the N outputs; 2) an output switching stage having M inputs and M outputs operable to connect selected ones of the M inputs to selected ones of the M outputs; 3) a multiplexer stage having a plurality of W-bit input channels and a W-bit output channel, wherein the output channel is coupled to the M inputs of the output switching stage; and 4) a removable core switching stage having N inputs adapted for coupling to the N outputs of the input switching stage and having M outputs adapted for coupling to a first input channel of the multiplexer stage. ## Claims ### Claim 1 A scalable switch fabric architecture comprising: an input switching stage having N inputs and N outputs operable to connect selected ones of said N inputs to selected ones of said N outputs; an output switching stage having M inputs and M outputs operable to connect selected ones of said M inputs to selected ones of said M outputs; a multiplexer stage having a plurality of W-bit input channels and a W-bit output channel, wherein said output channel is coupled to said M inputs of said output switching stage; and a removable core switching stage having N inputs adapted for coupling to said N outputs of said input switching stage and having M outputs adapted for coupling to a first input channel of said multiplexer stage. ### Claim 2 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein N=M. ### Claim 3 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein a second input channel of said multiplexer stage is adapted for coupling to M of R outputs of an output stage of a replacement core switching stage and said N outputs of said input switching stage are adapted for coupling to N of R inputs of an input stage of said replacement core switching stage, wherein the replacement core switching stage provides a parallel path around said removable core switching stage. ### Claim 4 (depends on 3) The scalable switch fabric architecture set forth in claim 3 wherein N=M. ### Claim 5 (depends on 4) The scalable switch fabric architecture set forth in claim 4 wherein R>N. ### Claim 6 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein said input switching stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said M inputs of said output switching stage to a selected one of said M outputs of said output switching stage. ### Claim 7 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein said input switching stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said N inputs of said removable core switching stage to a selected one of said M outputs of said removable core switching stage. ### Claim 8 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein said input switching stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said N inputs of said input switching stage to a selected one of said N outputs of said input switching stage. ### Claim 9 (depends on 1) The scalable switch fabric architecture set forth in claim 1 wherein said input switching stage receives ATM cell data and randomly connects ones of said N inputs of said input switching stage to ones of said N outputs of said input switching stage to thereby distribute said ATM cell data across said ones of said N input switching stage outputs. ### Claim 10 For use in a scalable switch fabric architecture comprising an input switching stage having N inputs and N outputs operable to connect selected ones of said N inputs to selected ones of said N outputs, an output switching stage having N inputs and N outputs operable to connect selected ones of said N output switching stage inputs to selected ones of said N output switching stage outputs, and a removable core switching stage having N inputs adapted for coupling to said N input switching stage outputs and having N outputs adapted for coupling to said N output switching stage inputs, a replacement core switching stage for replacing said removable core switching stage, said replacement core switching stage comprising: an input switching sub-stage having R inputs and R outputs operable to connect selected ones of said R inputs to selected ones of said R outputs, wherein N of said R inputs are adapted for coupling to said N input switching stage outputs; an output switching sub-stage having R inputs and R outputs operable to connect selected ones of said R output switching sub-stage inputs to selected ones of said R output switching sub-stage outputs, wherein N of said R output switching sub-stage outputs are adapted for coupling to said N output switching stage inputs; and a removable core switching sub-stage having R inputs adapted for coupling to said R input switching sub-stage outputs and having R outputs adapted for coupling to said R output switching sub-stage inputs. ### Claim 11 (depends on 10) The replacement core switching stage set forth in claim 10 wherein R>N. ### Claim 12 (depends on 10) The replacement core switching stage set forth in claim 10 wherein said input switching sub-stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said R inputs of said output switching sub-stage to a selected one of said R outputs of said output switching sub-stage. ### Claim 13 (depends on 10) The replacement core switching stage set forth in claim 10 wherein said input switching sub-stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said R inputs of said removable core switching sub-stage to a selected one of said R outputs of said removable core switching sub-stage. ### Claim 14 (depends on 10) The replacement core switching stage set forth in claim 10 wherein said input switching sub-stage receives ATM cell data comprising a cell header, wherein said cell header contains routing data operable to connect a selected one of said R inputs of said input switching sub-stage to a selected one of said R outputs of said input switching sub-stage. ### Claim 15 (depends on 10) The replacement core switching stage set forth in claim 10 wherein said input switching sub-stage receives ATM cell data and randomly connects ones of said R inputs of said input switching sub-stage to ones of said R outputs of said input switching sub-stage to thereby distribute said ATM cell data across said ones of said R input switching sub-stage outputs. ### Claim 16 For use in a scalable switch fabric architecture comprising an input switching stage having N inputs and N outputs operable to connect selected ones of the N inputs to selected ones of the N outputs, an output switching stage having N inputs and N outputs operable to connect selected ones of the N output switching stage inputs to selected ones of the N output switching stage outputs, and a removable core switching stage having N inputs adapted for coupling to the N input switching stage outputs and having N outputs adapted for coupling to the N output switching stage inputs, a method of replacing the removable core switching stage comprising the steps of: connecting a replacement core switching stage in parallel with the removable core switching stage, the replacement core switching stage comprising: an input switching sub-stage having R inputs and R outputs operable to connect selected ones of the R inputs to selected ones of the R outputs, wherein N of the R inputs are adapted for coupling to the N input switching stage outputs; an output switching sub-stage having R inputs and R outputs operable to connect selected ones of the R output switching sub-stage inputs to selected ones of the R output switching sub-stage outputs, wherein N of the R output switching sub-stage outputs are adapted for coupling to the N output switching stage inputs; and a removable core switching sub-stage having R inputs adapted for coupling to the R input switching sub-stage outputs and having R outputs adapted for coupling to the R output switching sub-stage inputs; and switching data traffic to the replacement core switching stage from the removable core switching stage; and removing the removable core switching stage. ### Claim 17 (depends on 16) The method set forth in claim 16 wherein R>N. ### Claim 18 (depends on 16) The method set forth in claim 16 wherein the input switching sub-stage receives ATM cell data comprising a cell header, wherein the cell header contains routing data operable to connect a selected one of the R inputs of the output switching sub-stage to a selected one of the R outputs of the output switching sub-stage. ### Claim 19 (depends on 16) The method set forth in claim 16 wherein the input switching sub-stage receives ATM cell data comprising a cell header, wherein the cell header contains routing data operable to connect a selected one of the R inputs of the removable core switching sub-stage to a selected one of the R outputs of the removable core switching sub-stage. ### Claim 20 (depends on 16) The method set forth in claim 16 wherein the input switching sub-stage receives ATM cell data comprising a cell header, wherein the cell header contains routing data operable to connect a selected one of the R inputs of the input switching sub-stage stage to a selected one of the R outputs of the input switching sub-stage. ### Claim 21 (depends on 16) The method set forth in claim 16 wherein the input switching sub-stage receives ATM cell data and randomly connects ones of the R inputs of the input switching sub-stage to ones of the R outputs of the input switching sub-stage to thereby distribute the ATM cell data across the ones of the R input switching sub-stage outputs.