Semiconductor memory device having a precharge device

Abstract

During a precharging period, first a bit line is precharged to a first potential and a sense amplifier is precharged to a second potential. Then, the bit line and the sense amplifier are connected together thorough a bit line transfer gate, and the precharge potential at the bit line is set to a third potential in accordance with a ratio of their capacitances. Following this, a word line is rendered active to connect a memory cell to the bit line. In accordance with the potential in the memory cell, a minute voltage is generated to the bit line, and the sense amplifier detects the minute voltage and amplifies it. Since the first and the second potentials differ from each other, the third potential can be an intermediate potential nearer the first potential. For example, when the first potential is set to a ground potential and the second potential is set to one available at a high potential power source, the third potential is set to shift toward the ground potential from half the power source potential. Since this potential is higher than the ground potential, a potential which is higher or lower than the third potential by the equivalent of the minute voltage is generated at a selected bit line. The sense amplifier, therefore, can employ the third potential at the opposite bit line as a reference potential.

Dependencies are inferred from the claim text.