Method for configuring FPGA memory planes for virtual hardware computation

A method of reconfiguring a dynamically reconfigurable programmable logic device (PLD), the PLD having a logic plane and a plurality of memory planes for modifying the functional characteristics of the PLD, the method comprising the steps of:

• a) providing a first memory plane including configuration data and user data for the PLD, the user data being stored in the first memory plane in a first predetermined spatial pattern;
• b) transferring the configuration data and the user data from the first memory plane to the logic plane;
• c) configuring the PLD in accordance with the configuration data transferred from the first memory plane;
• d) operating the PLD with the user data to generate new data;
• and
• e) saving the new data to one or more of the memory planes in a second predetermined pattern.

A method for carrying out a computation which includes a sequence of computation steps using a dynamically reconfigurable field programmable gate array (FPGA), the FPGA including a configurable logic plane and a plurality of memory planes, each memory plane including configuration data and user data, the user data being stored in a predetermined spatial pattern, the method comprising:

• a) attributing to each computation step an instruction, the instruction including the configuration data and user data stored in at least one of the memory planes;
• b) transferring the configuration data and the user data in step a) to the logic plane, the user data being arranged in a first predetermined spatial pattern;
• c) configuring the FPGA in accordance with the configuration data;
• d) operating the FPGA with the user data to produce new user data;
• e) saving the new user data to one or more of the memory planes in a second predetermined spatial pattern;
• and
• f) sequentially repeating steps b) through e) in accordance with the instructions stored in the memory planes to sequentially perform the computation steps.

A method for performing a virtual hardware computation in a programmable logic device (PLD), the PLD including a logic plane and a plurality of memory planes, the method comprising the steps of:

• determining the required steps of a computation task;
• for each required step, assigning a functional specification of a corresponding virtual instruction;
• browsing a virtual instruction library for the required virtual instructions;
• for each required step for which there is no virtual instruction in the virtual instruction library, if any, using the assigned functional specification and a timing specification to design new configuration data for the PLD to accomplish that step and thereby produce a new required virtual instruction;
• collecting and assembling all of the required virtual instructions as a sequence of virtual instructions, and wherein each virtual instruction is stored as configuration data and predefined input and output patterns of user data, the input pattern being before the instruction is carried out and the output pattern being after the instruction is carried out;
• determining whether the output pattern of one instruction matches the input pattern of a next consecutive instruction;
• and
• inserting a pattern manipulation instruction in the sequence of virtual instructions whenever the output pattern of one virtual instruction does not match the input pattern of the next consecutive virtual instruction.