Method of forming wafer alignment patterns

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising:

• forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another;
• and
• providing additional elevation steps in only a portion of at least one alignment pattern.

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising:

• forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another;
• and
• masking a first portion of at least one of the alignment patterns while subjecting a second portion of the at least one alignment pattern to processing conditions effective to change the second portion from the first portion.

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising:

• forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein at respective average elevations relative to the wafer, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another;
• and
• processing only a portion of at least one of the alignment patterns to change at least one of, a) elevation step degree of the elevation steps in the portion compared to elevation step degree of the elevation steps outside the portion in the one alignment pattern, or, b) the relative average elevation of the elevation steps in the portion from the average elevation of elevation steps outside of the portion in the one alignment pattern.

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein, the elevation steps in one pattern being different in degree from the elevation steps in the other pattern, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another.

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein at respective average elevations relative to the wafer, the elevation steps in one pattern being provided at a different average elevation relative to the wafer from the average elevation relative to the wafer that the other pattern of elevation steps is provided, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another.

A semiconductor processing method of forming wafer alignment patterns on a semiconductor wafer comprising:

• forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein, the two discrete alignment patterns being formed over different portions of the semiconductive wafer and not overlapping one another;
• and
• masking only one of the two alignment patterns while subjecting the other of the two alignment patterns to processing conditions effective to change the other pattern from the one pattern.