# US 6,040,583 A · Electron beam exposure method using a moving stage

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- Number: US 6,040,583 A
- Document ID: US6040583A
- Status: Granted
- Kind: A
- Application number: 09/083,095
- Filed: 1998-05-22
- Granted: 2000-03-21
- Earliest claimed: 1997-05-22
- Assignees: NEC Corporation
- Inventors: Naka Onoda
- Web page: https://patentgrep.com/patent/US6040583A

## CPC

- H01J 37/3174: {Particle-beam lithography, e.g. electron beam lithography}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H01J 2237/31764: Dividing into sub-patterns
- H01J 2237/31766: Continuous moving of wafer
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An electron beam exposure system has a continuous stage drive for driving a stage at a constant speed. Area of a semiconductor chip is divided into an array of unit meshes to calculate pattern density in each mesh. A group of meshes having an equal density level is combined as a sub-strip region having dimensions equal to or lower than the maximum width determined based on the ability of the electron beam exposure system.

## Claims

### Claim 1

An electron beam exposure method comprising the steps of:
dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strip regions having different widths; and
consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip,
wherein each said sub-strip region is modified based on sub-strip regions used in exposure during exposure for underlying patterns.

### Claim 2 (depends on 1)

An electron beam exposure as defined in claim 1, wherein said maximum width is an multiple of said width of each said sub-strip region.

### Claim 3

An electron beam exposure method comprising the steps of:
dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strips regions having different widths; and
consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip,
wherein said width of each sub-strip is determined based on a pattern density in said each sub-strip region.

### Claim 4

An electron beam exposure method comprising the steps of:
dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strips regions having different widths;
dividing the semiconductor chip into an array of unit meshes;
calculating a pattern density level in each of said unit meshes; and
consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip.

### Claim 5 (depends on 4)

An electron beam exposure method as defined in claim 4, each said sub-strip region comprises at least one said unit mesh.

### Claim 6 (depends on 5)

An electron beam exposure method as defined in claim 5 further comprising the step of controlling a stage speed based on the pattern density and the width.