Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

A method to prevent copper diffusion into dielectric layers in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:

• providing copper traces through an isolation layer overlying a semiconductor substrate;
• depositing a passivation layer overlying said copper traces and said isolation layer;
• depositing a dielectric layer overlying said passivation layer;
• depositing a cap layer overlying said dielectric layer;
• patterning said cap layer and said dielectric layer to expose the top surface of said passivation layer and to form interconnect trenches and via trenches for dual damascene interconnects overlying said copper traces;
• depositing a barrier layer overlying said passivation layer, said dielectric layer, and said cap layer;
• etching though said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said interconnect trenches and via trenches;
• etching through said passivation layer to expose the top surface of said copper traces;
• depositing a copper layer overlying said cap layer, said barrier layer, and said copper traces, and completely filling said interconnect trenches and said via trenches;
• and
• polishing down said copper layer to the top surface of said cap layer thereby completing said dual damascene interconnects in the manufacture of said integrated circuit device.

A method to prevent copper diffusion into dielectric layers in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device comprising:

• providing copper traces through an isolation layer overlying a semiconductor substrate;
• depositing a passivation layer of silicon nitride overlying said copper traces and said isolation layer;
• depositing a first dielectric layer overlying said passivation layer;
• depositing an etch stopping layer overlying said first dielectric layer;
• depositing a second dielectric layer overlying said etch stopping layer;
• depositing a cap layer overlying said second dielectric layer;
• patterning said cap layer, said second dielectric layer, said etch stopping layer, and said first dielectric layer to expose the top surface of said passivation layer and to form interconnect trenches and via trenches for dual damascene interconnects overlying said conductive traces;
• depositing a barrier layer of tungsten nitride overlying said passivation layer, said second dielectric layer, said etch stopping layer said cap layer, and said first dielectric layer;
• etching though said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said interconnect trenches and via trenches;
• etching through said passivation layer to expose the top surface of said copper traces wherein said barrier layer prevents copper sputtering onto said first dielectric layer and said second dielectric layer;
• depositing a copper layer by seedless electrochemical plating overlying said cap layer, said barrier layer, and said copper traces, and completely filling said via trenches and said interconnect trenches;
• and
• polishing down said copper layer to the top surface of said cap layer thereby completing said dual damascene interconnects in the manufacture of said integrated circuit device.