Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge
AssigneeABB Research Ltd.
InventorsMietek Bakowski, Ulf Gustafsson, Kurt Rottner, Susan Savage
Life of this patent
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Abstract
A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the higher doped conducting layer of the pn junction exhibits a charge profile with a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the main pn junction to a zero or almost zero total charge or charge density at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.
Claims9
A method of manufacturing a semiconductor component, said method comprising the steps of:
- forming a lower doped layer of the first conducting type in a silicon carbide wafer at the surface of the wafer;
- forming a higher doped anode layer of the second conducting type at the surface of and in said silicon carbide wafer, said lower doped layer and said anode forming a planar pn junction;
- masking an area of the wafer adjacent a prospective first zone not to be implanted;
- and
- implanting an implant in the exposed area of the wafer, thus forming a first junction termination extension zone of the second conducting type surrounding the anode, wherein the implantation dose is such that the effective sheet charge density in the first zone is at most equal to the characteristic sheet charge density Q.sub.0, corresponding to a doping such that the zone is completely depleted at full design voltage.
A method of manufacturing a semiconductor component, said method comprising the steps of:
- forming a lower doped layer of the first conducting type in a silicon carbide wafer at the surface of the wafer;
- forming a higher doped anode layer of the second conducting type at the surface of and in said silicon carbide wafer, said lower doped layer and said anode forming a planar pn junction;
- masking an area of the wafer outside said anode with a mask patterned with holes;
- and
- implanting areas of the wafer exposed by the holes in the mask with an implant, wherein the implantation dose is such that the effective sheet charge density in an innermost zone is at most equal to the characteristic sheet charge density Q.sub.0, corresponding to a doping such that the zone is completely depleted at full design voltage, thus forming spots of the second conducting type at the surface of the wafer, said spots constituting a junction termination extension having diminishing charge content in a radial direction away from the anode.
A method of manufacturing a semiconductor component, said method comprising the steps of:
- providing a silicon carbide wafer including a highly doped layer of a first conducting type, a lower doped layer of the first conducting type on top of the highly doped layer of the first conducting type, and a highly doped layer of a second conducting type forming an anode layer on top of the lower doped layer, said lower doped layer and said anode layer forming a planar pn junction;
- forming at least one junction termination zone by masking at least a portion of the wafer and implanting an implant in exposed areas of the wafer not covered by the mask, wherein the implantation dose is such that the effective sheet charge density in an innermost zone is at most equal to the characteristic sheet charge density Q.sub.0, corresponding to a doping such that the zone is completely depleted at full design voltage.
Dependencies are inferred from the claim text.